Extraction and interpretation or mobility in heavily doped junctionless transistors

Abstract

For the past few decades, the semiconductor industry has focussed on emerging transistor architectures to enable downscaling to meet the projections of Moore’s law. As a result, much interest has been directed towards transistors with simpler fabrication process and reduced Short Channel Effects (SCEs). Junctionless (JL) transistor, free from traditional pn junctions (due to same type of dopants in source, drain and channel), is considered as one of the promising architectures with suppressed SCEs as compared to a conventional Inversion Mode (IM) device. The heavily doped JL transistor (≥ 5×1018 cm-3) provides unique bulk conduction which is separated from the surface accumulation by flatband voltage (Vfb). Lowering the channel doping (< 5×1018 cm-3) transforms the JL transistor to an Accumulation Mode (AM) device with conduction mainly confined at surface of the silicon film.Due to the presence of two conduction mechanisms in JL transistor, an estimation of bulk (μbulk) and accumulation (μacc) mobility is essential to better understand the working of the device. However, to extract mobility in JL transistor, a careful analysis of the device architecture and associated physical phenomena related to the conduction mechanisms is required. Y-function (Ids/gm 0.5) is the most commonly used method for evaluating the mobility values in JL devices, which has the advantage of eliminating series resistance (Rsd) effects. However, the use of this method is limited to the determination of first order mobility reduction factor (1) and requires complex iterative process to determine the second order mobility reduction factor (2). Moreover, the conventional methods, which have been used to extract mobility parameters for IM device, are directly not applicable for JL transistor due to its different conduction mechanisms. Hence, the thesis examines the extraction methodology and interpretation of mobility in JL devices.In addition, the estimation of doping in JL transistor is equally important to distinguish it from AM devices, as well as to resolve the ambiguity that arises while estimating the actual postfabrication doping. The existing capacitance-voltage measurement techniques for estimating doping in JL transistors are not very straightforward and requires ac measurement set-up to obtaina meaningful value of doping levels. As dc analysis is always the first step in device characterization and facilities for the same are widely available, the thesis work focuses on a relatively simpler method to estimate doping through dc analysis. The key contribution of this thesis is to provide insights into the behaviour of JL transistor to further extract mobility parameters and doping levels by means of comprehensive physical device simulations. In this thesis, the extraction methodology to determine mobility parameters is modified to extract μbulk, μacc, 1 and 2 in a conventional JL transistor for a wide range of doping, oxide thicknesses, gate lengths and temperatures. μacc, which is immune to coulomb scattering at higher gate bias due to screening effect, is shown to exhibit higher values than μbulk. The mobility reduction factors in JL transistor are shown to be immune to vertical electric field as well as to Rsd, which is reflected on the negligible values of 1 and 2 as compared to IM and AM devices. However, as conventional JL transistors are heavily doped, the lower mobility can be improved by using Shell Doped (SD) JL architecture.The SD JL transistor consists of heavily doped shell at the front and back surfaces of the silicon film with centre being an undoped core region. The presence of an undoped core region along with screening effects in heavily doped shell enhances the carrier mobility in a SD JL transistor. By optimizing the shell depth (d) and shell doping (Nd), higher mobility can be achieved in these devices. For a wider core region, mobility reduction factors are enhanced due to an increase in series resistance as well as vertical field across the core and shell regions. Also, the impact of series resistance on bulk conduction has been investigated and the mobility reduction factor (1) has been analyzed through modified McLarty function.Finally, a new methodology has been developed to extract μbulk and doping in a conventional JL transistor by using dc characteristics. The method is based on utilizing bulk conduction in JL transistor by averaging the transconductance values between the limits of Vth and Vfb. Results highlight the wide applicability of the proposed method to estimate doping in long and short channel nMOS and pMOS JL transistors of different architectures (single gate, planar double gate, triple gate and cylindrical nanowire). Further, the proposed technique has been validated with the published experimental data available in the literature for triple gate JL transistor.