Enabling ultra-low power high density 6T SRAM using assisted design techniques

Abstract

The explosive growth of battery operated devices has made low-power design a priority in recent years. Moreover, embedded SRAM units have become an important block in modern SoCs. The increasing number of transistor count in the SRAM units and the surging leakage current of the MOS transistors in the scaled technologies have made the SRAM unit a power hungry block from both dynamic and static perspectives. The static power consumption is mainly due to the leakage current associated with the SRAM cells distributed in the array. Moreover, as supply voltage decreases to tackle the power consumption, the data stability of the SRAM cells have become a major concern in recent years.In embedded memories, Static Random Access Memory (SRAM) is considered as a critical technology enabler for a wide range of applications. However, with the scaling of complementary metal oxide semiconductor (CMOS) technology, the conventional SRAMs have failed to achieve the trade-off between system power and performance for the applications in electronic devices such as portable smartphones, laptops, field programmable gate arrays (FPGAs), IoT edged devices. Another challenge in ULV SRAM is the statistical process variations in transistor parameters such as threshold voltage (Vth), channel length (L), and mobility. Therefore, the statistical device variability in modern SRAM design has become a major concern, as it degrades the performance, reliability, and yield of the system. Moreover, the noise generated from threshold variation, process variation, half-select issue and multiple bit errors reduces the stability of SRAM cell. Therefore, the SRAM in-stability across process-voltage- temperature (PVT) values has also become a challenging issue.Source biasing is commonly used method for leakage reduction in deep sub-micron SRAM. However, application of such methods result into reduced stability of the SRAM bit cell. Moreover, reducing supply voltage and increasing process parameter variation put a limitation on such usage in deep sub-micron process. Present scheme describes a method to enhance stability while applying such data retention power gating to SRAM memory core. Method improves stability cross-corner/high-leakage conditions. This scheme is realized in 40 nm CMOS technology.In this scheme, at TT/0.85/25oC we could achieve the target leakage of 0.53pa/cell and ensuring six-sigma robustness for stability