Reduction in computational complexity using FPGA

Abstract

Usually, the extensive calculations done in real life like weather forecasting, science-related massive calculations take a lot of time, due to their complexity. Here in this project, as a preliminary example, we have tried to reduce the complexity as well as reduce clock cycles and calculation time, also to reduce the hardware if needed. This project is just an attempt to do so, by simply checking it on matrix multiplication and using directives to reduce clock cycles and equipment used, namely pipelining and unrolling. Vivado High-Level Synthesis (HLS) is being used for the simulation and creation of IP, while Vivado HLx for creating a block diagram by using the same IP which we produced at HLS. Further getting the multiplied output at Xilinx SDK, this has been used for the checking of the circuit created with its calculations, timing and other parameters, so that we can implement it physically later, only if the parameters match our requirement and modify it if needed. The board used in the project is the ZYBO board with a dual core arm cortex A9 processor present in it.