Error correction code and radiation hardening of digital circuits

Abstract

Moving towards deep-submicron technologies, packaging density of ICs is increasing, and thus, the number of storage elements is also increasing on an IC. Any data corruption in these storage elements leads to a huge amount of loss to companies. With decreasing technology nodes, the impact of radiation is increasing. Moreover, progress in technology is witnessing more timing violations with the age of the IC. This work is a study of error correction code techniques available and how to optimize it in terms of area, power, or delay. Error correction code techniques are used to obtain the correct data at the sender side; it has much application in automobile, medical, and space. It aims to compare the previously available techniques and finding the best one of them with some modification, mainly related to SEC-DAEC. In the proposed idea, several redundant bits requirement is the same as that of extended hamming code that is an add on advantage. And the next section consists of proposing an idea for the main gate, i.e., exclusive or. Implementation and designing of exclusive or based on pass transistor logic require less number of transistors than others. Data whole work is base on BCD-10 90nm technology, comparison done under different PVT corners to compare the various parameters like power dissipation, leakage, delay.