Novel hardware architecture for deep learning and computer vision

Abstract

An on-chip Neural Network Accelerator is becoming more popular in recent years as they have proved to be the one of best algorithms for various important detection and classification problem in image, speech and many more never ending applications in intelligent system design. While their on-chip presence is desired, their heavy computational demand stands still as barrier in making the next big steps in System on Chip design. Although hardware accelerators for artificial neural networks are often not very complex designs yet a tradition design approach have not been very fruitful as they often end up taking large silicon area and power. Researchers have indicated that fixed point processing element can result in significant reduction in resources utilization with a rather negligible impact on accuracy. An artificial neural network (ANN) is very popular for a many problems that are very difficult for the other computational model like image processing, pattern recognition, prediction and classification. The use of hardware architectures can have the more parallel structure of ANNs for desire optimize performance or reduce the cost of the implementation, particularly for applications demanding high parallel computation. However, many unique disadvantages is with the hardware platforms such as limitations with high data precision which has relation to hardware cost of the necessary computation, and the reconfigurability in the hardware implementation compared to software. Many error resilient applications can be approximated using multi-layer perceptron (MLP) with insignificant degradation in output quality on hardware platforms. Field programmable Gate Arrays (FPGAs) and Application Specification Integrated Circuit (ASICs), have edge over Graphics Processing Units (GPUs) on cost. This work presents a high in literature, the challenge is to investigate an ANN architecture, especially in pattern recognition with less hardware and high performance.