Please use this identifier to cite or link to this item:
https://dspace.iiti.ac.in/handle/123456789/18677
| Title: | Enabling Logic-in-Memory (LiM) Functionality with Junctionless FeFETs |
| Authors: | Nirala, Rohit Kumar Kranti, Abhinav |
| Issue Date: | 2026 |
| Publisher: | Institute of Electrical and Electronics Engineers Inc. |
| Citation: | Samant, N., Agavekar, A. A., Ganesh, D., Nirala, R. K., Gupta, M., & Kranti, A. (2026). Enabling Logic-in-Memory (LiM) Functionality with Junctionless FeFETs. 2026 International VLSI Symposium on Technology, Systems and Applications, VLSI TSA 2026 - Proceedings of Technical Papers. https://doi.org/10.1109/VLSITSA69131.2026.11527893 |
| Abstract: | Implementing logic (NOR/NAND) by utilizing the polarization of HZO ferroelectric (Fe) layer in field effect transistors (FETs) opens new possibilities for realizing logic operations within memory. Despite the relatively simpler fabrication process, junctionless (JL) Fe FETs exhibit a degraded State 1 and are unsuitable for implementing logic-in-memory (LiM). The drawback is addressed through a co-optimization of channel doping (1018 cm-3 instead of 1019 cm-3) and gate workfunction (midgap 4.7 eV rather than 5 eV) which enables NOR/NAND operations in JL FeFETs and their adaptation in LiM modules. © 2026 IEEE. |
| URI: | https://dx.doi.org/10.1109/VLSITSA69131.2026.11527893 https://dspace.iiti.ac.in:8080/jspui/handle/123456789/18677 |
| ISBN: | 979-833156238-0 |
| Type of Material: | Conference Paper |
| Appears in Collections: | Department of Electrical Engineering |
Files in This Item:
There are no files associated with this item.
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.
Altmetric Badge: