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| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Kumar, Sonu | en_US |
| dc.contributor.author | Lokhande, Mukul | en_US |
| dc.contributor.author | Vishvakarma, Santosh Kumar | en_US |
| dc.date.accessioned | 2026-08-18T10:35:34Z | - |
| dc.date.available | 2026-08-18T10:35:34Z | - |
| dc.date.issued | 2026 | - |
| dc.identifier.citation | Kumar, S., Pilipović, R., Lokhande, M., & Vishvakarma, S. K. (2026). E-NERVE: An Edge-Adaptive, NAF-Empowered, Resource-Efficient Versatile AI Inference Engine. IEEE Embedded Systems Letters. https://doi.org/10.1109/LES.2026.3716899 | en_US |
| dc.identifier.issn | 1943-0663 | - |
| dc.identifier.other | EID(2-s2.0-105045938307) | - |
| dc.identifier.uri | https://dx.doi.org/10.1109/LES.2026.3716899 | - |
| dc.identifier.uri | https://dspace.iiti.ac.in:8080/jspui/handle/123456789/18946 | - |
| dc.description.abstract | Non-linear activation functions (NAFs) account for only a small portion of deep neural network compute, yet provisioning dedicated activation hardware can increase area and create dark silicon in edge accelerators. This letter presents E-NERVE, a two-stage, runtime-adaptive inference engine that decouples MAC/FMA computation from activation evaluation using a shared MAC bank and a single time-multiplexed CORDIC-based activation core (V-ACT). V-ACT supports ReLU, Sigmoid, Tanh, and Softmax through runtime selection, while a PISO interface overlaps serial activation with the next tile’s MAC execution to avoid activation-induced throughput loss. Results show that activation reuse and MAC sharing reduce resource and energy overhead with accuracy degradation under 2.7% for selected models evaluated on CIFAR-100/ImageNet. For a 196:64:32:32:10 network (MNIST), the VC707 prototype consumes 0.267 W, while for a 28 nm ASIC, E-NERVE consumes 1.26 mm2, 0.38 W and achieves 6.78 GOPS/W with 98.32% accuracy. A Pynq-Z2 prototype achieves 154.6 ms latency at 0.25 W, validating the proposed latency-hiding activation reuse for resource-constrained edge inference. © 2009-2012 IEEE. | en_US |
| dc.language.iso | en | en_US |
| dc.publisher | Institute of Electrical and Electronics Engineers Inc. | en_US |
| dc.source | IEEE Embedded Systems Letters | en_US |
| dc.subject | Activation energy | en_US |
| dc.subject | Engines | en_US |
| dc.subject | Inference engines | en_US |
| dc.subject | Interfaces (computer) | en_US |
| dc.subject | Lutetium compounds | en_US |
| dc.subject | Network architecture | en_US |
| dc.subject | AI accelerator | en_US |
| dc.subject | Deep neural network | en_US |
| dc.subject | Fused multiply-accumulate | en_US |
| dc.subject | Modular architectures | en_US |
| dc.subject | Multiplyaccumulate (MAC) | en_US |
| dc.subject | Neural-networks | en_US |
| dc.subject | Non-linear activation function | en_US |
| dc.subject | Nonlinear activation functions | en_US |
| dc.subject | Reuse | en_US |
| dc.subject | Runtimes | en_US |
| dc.subject | Deep neural networks | en_US |
| dc.title | E-NERVE: An Edge-Adaptive, NAF-Empowered, Resource-Efficient Versatile AI Inference Engine | en_US |
| dc.type | Journal Article | en_US |
| Appears in Collections: | Department of Electrical Engineering | |
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