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https://dspace.iiti.ac.in/handle/123456789/18946
| Title: | E-NERVE: An Edge-Adaptive, NAF-Empowered, Resource-Efficient Versatile AI Inference Engine |
| Authors: | Kumar, Sonu Lokhande, Mukul Vishvakarma, Santosh Kumar |
| Keywords: | Activation energy;Engines;Inference engines;Interfaces (computer);Lutetium compounds;Network architecture;AI accelerator;Deep neural network;Fused multiply-accumulate;Modular architectures;Multiplyaccumulate (MAC);Neural-networks;Non-linear activation function;Nonlinear activation functions;Reuse;Runtimes;Deep neural networks |
| Issue Date: | 2026 |
| Publisher: | Institute of Electrical and Electronics Engineers Inc. |
| Citation: | Kumar, S., Pilipović, R., Lokhande, M., & Vishvakarma, S. K. (2026). E-NERVE: An Edge-Adaptive, NAF-Empowered, Resource-Efficient Versatile AI Inference Engine. IEEE Embedded Systems Letters. https://doi.org/10.1109/LES.2026.3716899 |
| Abstract: | Non-linear activation functions (NAFs) account for only a small portion of deep neural network compute, yet provisioning dedicated activation hardware can increase area and create dark silicon in edge accelerators. This letter presents E-NERVE, a two-stage, runtime-adaptive inference engine that decouples MAC/FMA computation from activation evaluation using a shared MAC bank and a single time-multiplexed CORDIC-based activation core (V-ACT). V-ACT supports ReLU, Sigmoid, Tanh, and Softmax through runtime selection, while a PISO interface overlaps serial activation with the next tile’s MAC execution to avoid activation-induced throughput loss. Results show that activation reuse and MAC sharing reduce resource and energy overhead with accuracy degradation under 2.7% for selected models evaluated on CIFAR-100/ImageNet. For a 196:64:32:32:10 network (MNIST), the VC707 prototype consumes 0.267 W, while for a 28 nm ASIC, E-NERVE consumes 1.26 mm2, 0.38 W and achieves 6.78 GOPS/W with 98.32% accuracy. A Pynq-Z2 prototype achieves 154.6 ms latency at 0.25 W, validating the proposed latency-hiding activation reuse for resource-constrained edge inference. © 2009-2012 IEEE. |
| URI: | https://dx.doi.org/10.1109/LES.2026.3716899 https://dspace.iiti.ac.in:8080/jspui/handle/123456789/18946 |
| ISSN: | 1943-0663 |
| Type of Material: | Journal Article |
| Appears in Collections: | Department of Electrical Engineering |
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