Please use this identifier to cite or link to this item: https://dspace.iiti.ac.in/handle/123456789/18969
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dc.contributor.authorSengupta, Anirbanen_US
dc.contributor.authorBhui, Nabenduen_US
dc.contributor.authorVerma, Vipinen_US
dc.date.accessioned2026-08-18T10:35:35Z-
dc.date.available2026-08-18T10:35:35Z-
dc.date.issued2026-
dc.identifier.citationSengupta, A., Bhui, N., & Verma, V. (2026). Detection of HLS-based Hardware Trojans using Logistic Regression Binary-Classifier. IEEE Embedded Systems Letters. https://doi.org/10.1109/LES.2026.3719415en_US
dc.identifier.issn1943-0663-
dc.identifier.otherEID(2-s2.0-105046732554)-
dc.identifier.urihttps://dx.doi.org/10.1109/LES.2026.3719415-
dc.identifier.urihttps://dspace.iiti.ac.in:8080/jspui/handle/123456789/18969-
dc.description.abstractLiterature has established that an attacker can exploit malicious/Trojan inserted high level synthesis (HLS) framework/tool for compromising hardware intellectual property (IP) designs. This paper presents a novel logistic regression (LR) based machine learning (ML) detection methodology capable of detecting the following seven state-of-the-art (SOTA) HLS Trojan variances: timer-sensitive trojan trigger based automated logic-transformation (TST-HT), time-bomb hardware Trojan (TB-HT), performance degradation hardware Trojan (PD-HT), battery exhaustion hardware Trojan (BE-HT), downgrade attack hardware Trojan (DA-HT), denial of service hardware Trojan (DoS-HT), and functional hardware Trojan (F-HT). The proposed detection technique is capable of very high accuracy with 0% FN and > 0% FP rates. © 2009-2012 IEEE.en_US
dc.language.isoenen_US
dc.publisherInstitute of Electrical and Electronics Engineers Inc.en_US
dc.sourceIEEE Embedded Systems Lettersen_US
dc.titleDetection of HLS-based Hardware Trojans using Logistic Regression Binary-Classifieren_US
dc.typeJournal Articleen_US
Appears in Collections:Department of Computer Science and Engineering

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