An analytical approach for designing ultra low power (ULP) subthreshold logic blocks with Germanium junctionless transistors

Abstract

For the past few decades, the semiconductor industry has focused on emerging transistor architectures to meet the projections of Moore’s law. As a result, much interest has been directed towards transistors with simpler fabrication process and reduced Short Channel Effects (SCEs). The semiconductor industry has continuously evolved in technological advancement and fabrication of Integrated Circuits (ICs) for High Performance (HP), Low Power (LP) and Ultra Low Power (ULP) logic applications. A miniaturized transistor with ideal subthreshold swing (SSwing) and a small extent of Drain Induced Barrier Lowering (DIBL) is prudent for ULP devices. However, due to the downscaling of gate length (Lg), SCEs can be observed in the characteristics of Metal Oxide-Semiconductor Field-Effect Transistors (MOSFETs). SCEs result in a decrease in threshold voltage (Vth) with decreasing Lg, higher drain induced barrier lowering, as well as deterioration in SSwing. A practical method adopted to reduce SCEs and to improve electrostatic controllability of gate over the channel region is by employing more number of gates in a transistor. Multi-gate junctionless (JL) transistors can be potential alternatives to conventional MOSFET for downscaling owing to the absence of traditional pn junctions, eased fabrication steps and thermal budgets, good control over the channel by multiple gates and improved immunity towards SCEs. Literature has shown the prospects of heavily doped (1019 cm-3 ) JL MOSFET over conventional MOSFET for LP logic devices as compared to HP logic device applications. A reasonably doped JL MOSFET (1018 cm-3 to 5×1018 cm-3 ) can additionally enhance LP transistor performance, decrease sensitivity and ease gate workfunction requirement. The use of wider underlap regions is also critical for LP devices. For a conventional JL MOSFETs, due to the same dopant type (ideally higher doping) across the semiconductor film, the elongation of depletion regions outside the channel region can occur in the off-state. Consequently, the effective channel length (Leff) becomes longer than Lg. An elongated Leff in the subthreshold operating region can reduce SCEs in these transistors and has the possibilities for LP devices while allowing miniaturization. This outstanding feature is present in predominantly all JL architectures. The thesis imparts exhaustive and purposeful approach to evaluate as well as alleviate SCEs in Germanium (Ge) Double Gate (DG) JL architectures (Ge DG JL with G-S/D underlap), by comprehensively focusing on effective gate length in the subthreshold region of operation which is important for ultra low power (ULP) applications. An emerging technology option should be able to support device for HP, LP and ULP applications. While Ge exhibiting higher mobility and can support HP and LP technologies catering to above threshold operation, the choice of ULP applications with Ge devices has been a bottleneck due to enhanced degree of SCEs in Ge based devices. This thesis also point towards important design parameters that can be utilized for better short channel immunity, and hence, improved architecture for Ge based DG JL transistor can find application in ULP subthreshold logic. The presented multi-region semi-analytical model can reasonably capture electrostatic channel potential at wider gate-underlap length and has shown good agreement with simulated data. A simplified analytical solution for subthreshold drain current can be utilized to evaluate threshold voltage, subthreshold swing and SCEs related parameters. The developed model results have shown acceptable agreement with simulation for predicting SCEs for varying underlap length, gate workfunction, channel doping, gate length and drain biases for Ge DG JL MOSFET. The results obtained from TCAD simulation and developed model suggest that channel doping together with underlap region decide the short channel performance of Ge DG JL transistor. An ULP CMOS inverter is implemented using Ge JL nMOS and pMOS DG devices. Universal gates, NAND and NOR, are also implemented in order to show the applicability of the developed approach for building subthreshold logic blocks. The sensitivity of subthreshold CMOS inverter is evaluated in terms of logic threshold (VLT), gain (AV), nominal high output voltage (VH) and nominal low output voltage (VL) which depends on the subthreshold swing of the devices. A variation in device parameters, Ge film thickness (TGe), Lg and GeON thickness (TGeON) affects VL, VH, VLT and AV more than other parameters considered in the analysis. An in-depth analysis focusing on Ge DG JL transistors for subthreshold logic has been presented in this thesis.