High speed synchronous serdes transceiver design

Abstract

Today due to advancement in wireless and wireline technologies, the requirement of high-speed data rate devices are increasing. The network devices should be capable of handling and process high-speed data signal reliably with minimum electromagnetic interference(EMI) and bit error rates(BER).The most promising solution for these requirements is SerDes transceiver design, which can handle high-speed data transfer. A synchronous on-chip SerDes (Serializer and Deserializer) is proposed using current mode logic (CML) technique. Instead of using multiplexers (MUX) for designing serializer, CML based double edge triggered (DETFF) flip-flops is used. Deserializer uses both positive and negative edge triggered CML – based D flip flops. The clock and data recovery circuit using phase locked loop(PLL) consumes more power than PLL - less clock and data recovery circuit. Hence a novel design of PLL-less clock and data recovery circuit is used using 3 level encoder-decoder technique. Apart from clock and data recovery, it also eliminates the need of transmit (feed forward) equalizer and receiver(decision feedback) equalizer. A 3 mm lossy transmission line is used for transmission of serialized stream. This work is implemented in UMC 65 nm technology.In this work, a total power consumption of 44.03%, and the data rate of 25% is improved in designing of serializer and deserializer and an power consumption of 62%, and data rate of 12% is improved for the design of SerDes using a new proposed Phase Locked Loop(PLL) less clock and data recovery circuit than recent works. SerDes is used in various applications which include stackable Ethernet switch expansion, rackto- rack, shelf-to-shelf datacom/telecom interconnect, video/camera links, base stations, automotive imaging/video, sensor systems telecom, add-drop multiplexers, pseudo-optical switches etc.