Bit-serial computing technique based efficient deep neural network accelerator

Abstract

Contemporary hardware implementations of deep neural networks face the burden of excess area requirement due to resource-intensive elements such as a multiplier. A semi-custom ASIC approach-based VLSI circuit design of the multiply-accumulate unit in a deep neural network faces the chip area limitation. Therefore an area and power-efficient architecture for the multiply-accumulate unit is imperative to down the burden of excess area requirement for digital design exploration. The present work addresses this challenge by proposing an efficient processing and bit-serial computation based multiply-accumulate unit implementation. The proposed architecture is verified using simulation output and synthesized using Synopsys design vision at 180nm and 45nm technology and extracted all physical parameters using Cadence Virtuoso. At 45nm, design shows 34.35% less area-delay-product (ADP). It shows improvement by 25.94% in area, 35.65% in power dissipation, and 14.30% in latency with respect to the state-of-the-art multiply-accumulate unit design. Furthermore, at lower technology node gets higher leakage power dissipation. In order to save leakage power, we exploit the power-gated design for the proposed architecture. The used coarse-grain power gating technique saves 52.79% leakage/static power with minimal area overhead. The system-level performance of MAC has evaluated using LeNet architecture which is implemented on the FPGA board to validate the performance parameters impact of the proposed multiply-accumulate unit. The architecture with the proposed multiply accumulate unit saved 49.39% look-up table utilization for multiply-accumulate unit and 20% overall look-up table utilization compared to MAC with Xilinx multiplier and adder IP. The proposed architecture over performed for critical time delay compared to the state-of-the-art.