Ultra - low power SRAM design in nanoscale CMOS and multigate FinFET technologies

Abstract

Embedded SRAMs are a critical component in modern digital systems, and their role is preferentially increasing. Highly energy-constrained systems (e.g. implantable biomedical devices, multimedia handsets, wearable devices etc.) are an important class of applications driving ultra-lowpower SRAMs. As a result, SRAMs strongly impact the overall power, performance, and area, and, in order to manage these severely constrained trade-offs, they must be specially designed for target applications. A novel 8-transistor (8T) static random access memory cell with improved data stability in subthreshold operation is designed. The proposed single-ended with dynamic feedback control 8T SRAM cell enhances the static noise margin (SNM) for ultra-low power supply. It achieves write SNM of 1.4x and 1.28x as that of iso-area 6T and read-decoupled 8T (RD-8T), respectively, at 300mV power supply. The standard deviation of write SNM for 8T cell is reduced to 0.4x and 0.56x as that for 6T and RD-8T, respectively. It also possesses another striking feature of high read SNM ~2.33x, 1.23x and 0.89x as that of 5T, 6T and RD-8T, respectively. The cell has hold SNM of 1.43x, 1.23x and 1.05x as that of 5T, 6T and RD-8T, respectively. The write time is 71% less than that of the single-ended asymmetrical 8T cell. The proposed 8T consumes write power of 0.72x, 0.6x and 0.85x that of 5T, 6T and iso-area RD-8T, respectively. The read power is 0.49x of 5T, 0.48x of 6T and 0.64x of RD-8T. The power/energy consumption of 1kb 8T SRAM array during read and write operations is 0.43x and 0.34x, respectively of 1kb 6T array. These features enable ultra-low power applications of the proposed 8T cell.A novel single-ended boost-less (SE-BL) 7T static random access memory (SRAM) cell with high write-ability and reduced read failure is proposed. The proposed 7T cell utilizes dynamic feedback cutting (DFC) during write/read operation. The 7T also uses dynamic read decoupling during a read operation to reduce the read disturb. The proposed 7T writes “1” through one NMOS and Writes “0” using two NMOS pass transistors. The 7T has mean (μ) of 222.3mV (74.1% of supply voltage) for write trip point (WTP) where 5T fails to write “1” at 300mV. It gives mean (μ) of 276mV (92% of supply voltage) for read margin while 5T fails due to read disturb at 300mV. The hold static noise margin of 7T is maintained close to as that of 5T. The read delay of 7T is 22.5% lower than 5T and saves 10.8% read power consumption. It saves 36.9% read and 50% write power consumption, as compared to conventional 6T. The techniques used by the proposed 7T SRAM cell allow it to operate at ultra-low voltage (ULV) supply without any write assist in UMC 90nm technology node. A 20nm FinFET based 7T SRAM cell is presented. For the proposed 7T, the mean and standarddeviation (μ/σ) ratio of hold static noise margin is 6.3% higher than that of conventional iso-area 5T at 0.2V VDD. The 7T has 28.55% higher μ/σ of read margin as that of 5T at 0.4V VDD. The write static noise margin of 7T is ~50% of VDD for all VDD values whereas 5T fails to write. During write ‘0’, the proposed cell consumes only 0.11x power as that of 5T at 0.8V VDD. The read operation of 7T consumes 0.34x lesser power than 5T during a read operation for all values of bit-line capacitances at 0.2V VDD. At 0.2V VDD, the 7T has 0.46x lower write ‘0’ delay than that of 5T. The write delay of 7T is 0.32x lower than that of 5T at 0.8V VDD. A novel differential 8T SRAM cell is proposed. This novel 8T structure results in 6% higher HSNM and 66% higher WSNM compared to a conventional 6T cell. The proposed 8T cell allows 29% faster write operation compared to 6T with 20% lower leakage power. The proposed 8T cell can sustain 7 sigma variations in process parameters in 14nm FinFET technology. Voltage scaling and read port decoupling techniques are used. Minimum sized transistors are used to reduce the area overhead due to 10T configuration. With new circuit topology of the proposed 10T cell we have found the RSNM of the proposed 10T cell is 4.95x of 6T RSNM, has 6.42% higher HSNM than 6T, the write power is reduced by 50% and the read power is reduced by 35%. Moreover, at 300mV power supply, the conventional 6T shows the write failure while 10T gives 142mV write trip point value. We extend our discussion and present results on the advantages of using charge sharing to increase the sensing speed using a single-ended read configuration. The charge sharing scheme shows 6.8% to 9.7% performance improvement over the conventional sensing scheme. All these schemes, topologies and analyses can be helpful to design ultra-low power SRAMs thatcan be useful for implantable biomedical devices, multimedia handsets, mobile phones etc.