Variability aware design of SRAM in conventional and non-conventional MOS technologies : a sense amplifier perspective

Abstract

Continuing progress and integration levels in silicon technologies make possible complete end user systems consisting of multi cores on a single chip targeting either embedded or high performance computing. To relentlessly meet this ubiquitous need recently evolved multicore architectures need large embedded memories to support high bandwidth and computational requirements. Therefore, for the foreseeable future, static random access memory (SRAM) will likely remain the embedded memory technology of choice for many microprocessors and systems on chips (SoCs) due to its speed and compatibility with standard logic processes. For these reasons, it is considered to be highly promising and attracted considerable research attention towards optimizing its reliability, power and speed. Consequently, designing energy efficiency SRAMs is one of the key components for energy-efficient systems. However, without new paradigms of energy efficient designs, producing embedded SRAM capable of meeting the computing storage and communication demands of the emerging applications will be unlikely. Access time and power consumption of memories is largely determined by sense amplifier (SA) design. If the SA-enable (SEN) signal is asserted early, the sense amplifier cannot amplify the small voltage difference correctly. The overhead of access time and power consumption is increased if the SEN is asserted late. Therefore, the optimum timing for SEN signal is critical for a high-speed and low-power SRAM design. The minimum required bitline swing is often limited by the sense amplifier offset voltage (VOS). The SA offset voltage, is the minimum voltage difference between the bitlines, effective to cause the output signal to rail to a specified state. Therefore if higher is the offset of sense amplifier, higher will be the required differential voltage, resulted in higher bitline swing (More power) and delayed SEN enabling (Slow Memory). With technology scaling toward the physical limit, process variations become a growing concern in sense amplifier designs. Because, continued process scaling tends to cause increases in the input referred offset of sense amplifiers topologies. This is largely due to the overall increase in local (e.g. within-die) process variation due to mechanisms such as lithographic variation and random doping fluctuation (RDF). These localvariations cause the threshold voltage (VTH) of transistors with identical layout to be distributed normally, and the standard deviation of the VTH distribution is proportional to 1/ (WL) 1/2. Therefore, nanoscale technologies unveiled two significant challenges to the design of high-speed and reliable SRAMs. The first challenge is the process variation which threatens the reliability by affecting the sensing circuit’s sensitivity. This effect demands larger signal magnitudes, which deteriorate the speed as well as power consumption. The second challenge is the variation of the cell current (ICELL), which reduces the worst case cell current that drives the bitline. In effect, this reduction demands a longer wordline activation time to ensure sufficient bitline voltage swing for correct sensing. The wordline activation time directly influences the cell data stability. A long wordline activation time can affect the noise margin. Indeed, as VDD is scaled down, decreasing memory cell current issues concerning differential current degradation in the current sense amplifier become severe. The objective of this work was to study the impact of device variability due to scaling of MOS devices on SRAM performance matrix specially variability induced failure rate of SRAM, overall memory power dissipation, and read latency of SRAM. We analyzed these attributes from sense amplifier perspectives. In view of the modern CMOS process fin shaped field effect transistors (FinFET) based sense amplifier design is explored due to its superior gate control, improved electrostatic integrity, lower variability, satisfactory scalability and feasibility for mass production of post-22-nm nodes. In this thesis we study the double-gate FinFET sense amplifier technology-circuit design space to understand the interplay of device variability, sense amplifier offset, access time, and variability induced failure rate. Further, in this work, a novel, high-performance and robust sense amplifier design is presented for small ICELL SRAM, using FinFET in 22-nm technology. The technique offers data-line-isolated current sensing approach. Compared with the conventional current sense amplifier (CCSA) and hybrid SA (HSA), the proposed current feed-SA (CF-SA) demonstrates 2.15× and 3.02× higher differential current, respectively, for VDD of 0.6V. We also study the impact of the number of Fins on the performance of FinFET sense amplifiers and analyze current ratio amplification factor (CRA) to make even more interesting.