Key-triggered hash-chaining-based encoded hardware steganography for securing DSP hardware accelerators

Abstract

This chapter describes a multi-encoding-driven key-triggered hash-chaining-based hardware steganography approach for securing digital signal processing (DSP) hardware accelerators which uses multiple layers of encoding and key-based parallel switch blocks (SBs) to drive multiple secure hash-chaining blocks in the algorithm. The presented approach is highly robust against fraud ownership claim and piracy threats. The chapter is organized as follows: Section 7.1 provides some introduction to the research problem, followed by some discussion on other selected approaches in Section 7.2; Section 7.3 describes the presented hash-chaining-based hardware steganography approach. Section 7.4 presents the design process of securing finite impulse response (FIR) filter using this hardware steganography process; Section 7.5 presents the KHC-stego tool of this corresponding key-triggered hash-chaining hardware steganography approach; Section 7.6 discusses the analysis on case studies; Section 7.7 concludes the chapter, while Section 7.8 presents some exercise for readers. © The Institution of Engineering and Technology 2021.