Cryptography-driven IP steganography for DSP hardware accelerators

Abstract

The chapter describes a cryptography-driven intellectual property (IP) steganography process for securing hardware accelerators. The chapter focusses on hardware accelerators that are used popularly in digital signal processing (DSP) applications for modern electronics systems/products. A detailed elaboration on the salient features of cryptography-driven IP steganography process, its differences from DSP watermarking approaches, other hardware steganography approaches, details of secret steganography constraint generation process, embedding process, detection process and details on case studies have been provided. The chapter is organized as follows: Section 2.1 discusses the background of this topic; Section 2.2 presents the contemporary approaches for securing hardware accelerators. Section 2.3 presents the crypto-based steganography process for securing hardware accelerators; Section 2.4 introduces a new crypto-stego tool for securing hardware accelerators; Section 2.5 presents the case studies on DSP hardware accelerators; Section 2.6 concludes the chapter; Section 2.7 provides some exercise for the readers. © The Institution of Engineering and Technology 2021.