Multi-level watermark for IP protection

Abstract

The chapter describes a multi-level watermarking process for intellectual property (IP) cores that leverages the electronic-system level (ESL) and register-transfer level (RTL). A detailed elaboration is provided on the salient features of this multilevel watermarking approach followed by its encoding technique, embedding process, detection process and, finally, implementation details using case studies. The chapter is organized as follows: Section 5.1 discusses the abstraction levels of a digital design followed by some IP protection basics; Section 5.2 introduces some of the prior works in this domain; Section 5.3 presents the salient features and advantages of a multi-level watermarking process; Section 5.4 explains the signature-embedding process for digital signal processor (DSP) cores; Section 5.5 discusses the design process of a multi-level watermarked IP core using a finite impulse response (FIR) filter; Section 5.6 presents the signature detection details of a multi-level watermark; Section 5.7 presents an analysis based on case studies; Section 5.8 concludes the chapter. © The Institution of Engineering and Technology 2020.