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https://dspace.iiti.ac.in/handle/123456789/4573
Title: | Securing IP Cores in CE Systems using Key-driven Hash-chaining based Steganography |
Authors: | Rathor, Mahendra Mishra, Vipul Kumar Sengupta, Anirban |
Keywords: | Digital signal processing;Digital signal processors;Intellectual property core;Design chains;Digital signal processors (DSP);Hash chaining;High securities;Integrated circuits (ICs);Performance data;Reliability and safeties;Secret information;Steganography |
Issue Date: | 2020 |
Publisher: | IEEE Computer Society |
Citation: | Rathor, M., Sarkar, P., Mishra, V. K., & Sengupta, A. (2020). Securing IP cores in CE systems using key-driven hash-chaining based steganography. Paper presented at the IEEE International Conference on Consumer Electronics - Berlin, ICCE-Berlin, , 2020-November doi:10.1109/ICCE-Berlin50680.2020.9352192 |
Abstract: | Digital signal processor (DSP) intellectual property (IP) cores are the underlying hardware responsible for high performance data intensive applications. However an unauthorized IP vendor may counterfeit the DSP IPs and infuse them into the design-chain. Thus fake IPs or integrated circuits (ICs) are unknowingly integrated into consumer electronics (CE) systems, leading to reliability and safety issues for users. The latent solution to this threat is hardware steganography wherein vendor's secret information is covertly inserted into the design to enable detection of counterfeiting. A key-regulated hash-modules chaining based IP steganography is presented in our paper to secure against counterfeiting threat. The proposed approach yielded a robust steganography achieving very high security with regard to stego-key length than previous approaches. © 2020 IEEE. |
URI: | https://doi.org/10.1109/ICCE-Berlin50680.2020.9352192 https://dspace.iiti.ac.in/handle/123456789/4573 |
ISBN: | 9781728158853 |
ISSN: | 2166-6814 |
Type of Material: | Conference Paper |
Appears in Collections: | Department of Computer Science and Engineering |
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