High Level Synthesis Methodology for Exploring Loop Unrolling Factor and Functional Datapath

Abstract

High level synthesis (HLS) forms the backbone of design process for digital signal processing (DSP) kernels. Further design space exploration (DSE) in HLS is quite challenging. However, DSE process becomes more intricate for control DSP kernels (with loops) due to the involvement of a complex variable affecting design area/power and latency called' loop unrolling factor'. This paper presents a process for exploring loop unrolling factor and functional datapath functional units concurrently using genetic algorithm (GA) that meets the user specified design constraints. Results have been tested on variety of DSP kernels along with the sensitivity analysis of GA. The presented approach has been successfully able to converge on optimal solutions in most cases for the tested DSP kernels. © 2018 IEEE.