Please use this identifier to cite or link to this item:
https://dspace.iiti.ac.in/handle/123456789/4634
Title: | Multi-phase watermark for IP core protection |
Authors: | Sengupta, Anirban Roy, Dipanjan |
Keywords: | Abstracting;Intellectual property core;Abstraction level;Architectural synthesis;Conflict Resolution;Levels of abstraction;Low overhead;Single phase;Watermarking |
Issue Date: | 2018 |
Publisher: | Institute of Electrical and Electronics Engineers Inc. |
Citation: | Sengupta, A., & Roy, D. (2018). Multi-phase watermark for IP core protection. Paper presented at the 2018 IEEE International Conference on Consumer Electronics, ICCE 2018, , 2018-January 1-3. doi:10.1109/ICCE.2018.8326058 |
Abstract: | Embedding a strong watermark is sufficient to prove IP core ownership during conflict resolution process. However, watermark embedded at lower levels of abstraction may incur design overhead and complexity. Further, watermark embedded at lower level of design does not help to protect a reusable IP core generated during architectural synthesis (at higher abstraction level). This paper presents a low overhead multi-phase watermark implanted during architectural synthesis that is more robust and tamper tolerant than existing single phase watermarks at higher abstraction level. The average reduction percentage of proposed multi-phase watermark approach compared to other related approach in terms of area, latency and cost is greater than 6%, 5% and 6% respectively. © 2018 IEEE. |
URI: | https://doi.org/10.1109/ICCE.2018.8326058 https://dspace.iiti.ac.in/handle/123456789/4634 |
ISBN: | 9781538630259 |
Type of Material: | Conference Paper |
Appears in Collections: | Department of Computer Science and Engineering |
Files in This Item:
There are no files associated with this item.
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.
Altmetric Badge: