Please use this identifier to cite or link to this item: https://dspace.iiti.ac.in/handle/123456789/4688
Title: Exploration of optimal multi-cycle transient fault secured datapath during high level synthesis based on user area-delay budget
Authors: Sengupta, Anirban
Keywords: Budget control;Data flow analysis;Data flow graphs;Graphic methods;Particle swarm optimization (PSO);Control data flow graphs;Delay overheads;Design solutions;Design space exploration;Optimal solutions;Primary functions;Transient faults;User constraints;High level synthesis
Issue Date: 2015
Publisher: Institute of Electrical and Electronics Engineers Inc.
Citation: Sengupta, A., & Sedaghat, R. (2015). Exploration of optimal multi-cycle transient fault secured datapath during high level synthesis based on user area-delay budget. Paper presented at the Canadian Conference on Electrical and Computer Engineering, , 2015-June(June) 69-74. doi:10.1109/CCECE.2015.7129162
Abstract: Detecting error or producing correct output is the primary function of a fault secured system. In the context of multi-cycle transient faults, design space exploration (DSE) of an optimal fault secured datapath based on user constraints of area and delay during high level synthesis (HLS) is considered notorious. This is derived from the fact that generation of a user budget bounded multi-cycle transient fault secured datapath may not be possible for every type of candidate design solution produced during exploration. Additionally, insertion of inapt cut to optimize delay overhead associated with fault security in most cases may not yield optimal solutions in the context of user constraints/budgets. This paper resolves the above problems which has not been addressed in the literature so far by proposing the following novelties: (a) fault secured particle swarm optimization (PSO) driven DSE methodology (b) Techniques to handle multi-cycle transient faults during DSE (c) Schemes for choosing pertinent edges for inserting cut (s) in scheduled Control Data Flow Graph (CDFG) that optimizes the delay overhead associated with fault security. Results of the proposed approach indicated that the fault secured solution found comprehensively minimizes the final cost as well as satisfies the conflicting user budgets. Further, the final fault secured solution yielded is significantly lower in cost compared to solutions obtained through recent similar approaches. © 2015 IEEE.
URI: https://doi.org/10.1109/CCECE.2015.7129162
https://dspace.iiti.ac.in/handle/123456789/4688
ISBN: 9781479958276
ISSN: 0840-7789
Type of Material: Conference Paper
Appears in Collections:Department of Computer Science and Engineering

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