Please use this identifier to cite or link to this item: https://dspace.iiti.ac.in/handle/123456789/4745
Title: A methodology for self correction scheme based fast multi criterion exploration and architectual synthesis of data dominated applications
Authors: Sengupta, Anirban
Keywords: Architectural synthesis;Architecture synthesis;Circuit interconnections;Design space exploration;High-level synthesis;Multi-Criterion;rapid;Self-correction;Algorithms;Automation;Data flow analysis;Data flow graphs;Information science;Natural resources exploration;Benchmarking
Issue Date: 2013
Citation: Sengupta, A. (2013). A methodology for self correction scheme based fast multi criterion exploration and architectual synthesis of data dominated applications. Paper presented at the Proceedings of the 2013 International Conference on Advances in Computing, Communications and Informatics, ICACCI 2013, 430-436. doi:10.1109/ICACCI.2013.6637210
Abstract: This paper introduces a novel methodology for self correction scheme based fast multi criterion exploration and automated architectural synthesis of data dominated applications. The four major novel contributions of the paper are as follows: a) Introduction of two new algorithms that is able to efficiently tackle conditions when the user provided high level constraint values are invalid in nature. This is done using an algorithm to validate the user constraints as well as an algorithm to self rectify the user constraints value automatically if the final Pareto optimal set is found vacant b) Introduction of a novel input format for data flow graph applications and its custom representation c) Introduction of a novel algorithm that is capable to perform automated architectural synthesis using techniques to convert from scheduling to circuit interconnection phase. These new algorithms have been incorporated into a multi criterion design space exploration framework d) New experimental results are reported for the results obtained through proposed multi criterion exploration approach and its speed improvement compared to recent approach. The proposed method, when applied to High Level Synthesis (HLS) benchmarks, yielded speed improvement of more than 90 % compared to recent DSE approach without sacrificing quality of final solution. © 2013 IEEE.
URI: https://doi.org/10.1109/ICACCI.2013.6637210
https://dspace.iiti.ac.in/handle/123456789/4745
ISBN: 9781467362153
Type of Material: Conference Paper
Appears in Collections:Department of Computer Science and Engineering

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