Please use this identifier to cite or link to this item: https://dspace.iiti.ac.in/handle/123456789/4843
Title: Facial Biometric for Securing Hardware Accelerators
Authors: Sengupta, Anirban
Rathor, Mahendra
Keywords: Biometrics;Digital signal processing;Comparative analysis;Digital evidence;Digital signal processing (DSP);DSP application;Hardware accelerators;Multimedia Intellectual Property;Qualitative and quantitative analysis;Security methodologies;Hardware security
Issue Date: 2021
Publisher: Institute of Electrical and Electronics Engineers Inc.
Citation: Sengupta, A., & Rathor, M. (2021). Facial biometric for securing hardware accelerators. IEEE Transactions on very Large Scale Integration (VLSI) Systems, 29(1), 112-123. doi:10.1109/TVLSI.2020.3029245
Abstract: This article presents a novel facial biometrics-based hardware security methodology to secure hardware accelerators [such as digital signal processing (DSP) and multimedia intellectual property (IP) cores] against ownership threats/IP piracy. In this approach, an IP vendor's facial biometrics is first converted into a corresponding facial signature representing digital template, followed by embedding facial signature's digital template into the design in the form of secret biometric constraints, thereby generating a secured hardware accelerator design. The results report the following qualitative and quantitative analysis of the proposed biometric fingerprint approach: 1) impact of five different facial biometrics constraints on probability of coincidence (Pc) metric (indicating strength of digital evidence). The proposed approach achieves a very low Pc value in the range of 1.54E-5 to 2.01E-5; 2) impact of different facial feature set of a facial biometric image on total number of generated secret constraints and Pc. As evident, for all facial feature sets implemented, Pc ranges between 3.31E-4 and 2.01E-5; and 3) comparative analysis of proposed approach with recent work, for different DSP applications and five different facial biometric images, in terms of Pc. As evident, the proposed approach achieves significantly lower Pc, compared with recent work. © 1993-2012 IEEE.
URI: https://doi.org/10.1109/TVLSI.2020.3029245
https://dspace.iiti.ac.in/handle/123456789/4843
ISSN: 1063-8210
Type of Material: Journal Article
Appears in Collections:Department of Computer Science and Engineering

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