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https://dspace.iiti.ac.in/handle/123456789/4869
Title: | Removal Attacks on Logic Locking and Camouflaging Techniques |
Authors: | Mazumdar, Bodhisatwa |
Keywords: | Boolean functions;Cryptography;Formal logic;Hardware security;Integrated circuits;Internet protocols;Locks (fasteners);Logic gates;Network security;Reverse engineering;Boolean satisfiability;IP networks;Layout;Logic locking;Security;Computer circuits |
Issue Date: | 2020 |
Publisher: | IEEE Computer Society |
Citation: | Yasin, M., Mazumdar, B., Sinanoglu, O., & Rajendran, J. (2020). Removal attacks on logic locking and camouflaging techniques. IEEE Transactions on Emerging Topics in Computing, 8(2), 517-532. doi:10.1109/TETC.2017.2740364 |
Abstract: | With the adoption of a globalized and distributed IC design flow, IP piracy, reverse engineering, and counterfeiting threats are becoming more prevalent. Logic obfuscation techniques including logic locking and IC camouflaging have been developed to address these emergent challenges. A major challenge for logic locking and camouflaging techniques is to resist Boolean satisfiability (SAT) based attacks that can circumvent state-of-the-art solutions within minutes. Over the past year, multiple SAT attack resilient solutions such as Anti-SAT and AND-tree insertion (ATI) have been presented. In this paper, we perform a security analysis of these countermeasures and show that they leave structural traces behind in their attempts to thwart the SAT attack. We present three attacks, namely 'signal probability skew' (SPS) attack, 'AppSAT guided removal (AGR) attack, and 'sensitization guided SAT' (SGS) attack', that can break Anti-SAT and ATI, within minutes. © 2013 IEEE. |
URI: | https://doi.org/10.1109/TETC.2017.2740364 https://dspace.iiti.ac.in/handle/123456789/4869 |
ISSN: | 2168-6750 |
Type of Material: | Journal Article |
Appears in Collections: | Department of Computer Science and Engineering |
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