Investigation of drain extension feature in a double-gate silicon based tunnel fet for low power SoC applications

Abstract

The conventional metal oxide semiconductor field effect transistor (MOSFET) is approaching the scaling limit because of its subthreshold slope (SS), governed by thermionic emission-carrier diffusion over a thermal barrier being limited to 60 mV/decade at room temperature. This limitation is challenging for supply voltages below 1 V because of incremental short channel effects (SCEs) and leakage currents making it unsuitable for analog/RF applications. This generates a necessity for the ultralow power and energy-efficient transistor with SS below 60 mV/decade for future generation of integrated circuits (IC). Therefore, the tunnel field-effect transistor (TFET) is being explored as an attractive alternative to the MOSFET for low-power applications. Unlike MOSFETs, TFETs are not limited by the thermionic emission constraint since the carrier injection from source to channel in the TFET is by tunneling, which could provide SS lower than 60 mV/decade limits of the conventional MOSFETs. This enables low standby leakage currents and further scaling of supply voltage (Vdd) and makes it suitable for low power system on chip (SoC) applications which contains analog/RF and digital blocks. Due to different conduction concept, the sensitivity of the TFET’s analog/RF characteristics to the variation in the technology parameter will be different as compared to conventional MOSFETs. Therefore, there is need to characterize the novel device for analog/RF performance before placing into the SoC design. In this way my research topic entitled “investigation of drain extension feature in a double gate Silicon tunnel FET for low power SoC applications” dedicate to investigate TFET performance for various device engineering and to unfold analog/RF behavior.For this purpose, we present lateral asymmetric drain (LAD) doping effect on a double gate tunnel fieldeffect transistor (DG-TFET) and its influence on device RF performances. The LAD doping profile improves technological issues such as suppresses the ambipolar behavior, improves OFF-state current, and reduces the gate–drain capacitance. Along with that, this addition of LAD doping in the drain extension region also improves RF figures of merit. Further, the lateral abruptness effect for different gate lengths is also checked by ac small-signal simulation to provide more insights related to the influence of lateral abruptness on RF performance. The result demonstrates the feasibility of lateral asymmetric drain as a way to improve the RF figures of merit for low-power design application significantly. Further we, follow the influence of LAD doping on RF performance, present the effect of its variation in DG-TFET reliability and its impact on analog/RF characteristics. For this, we report a quantitative understanding of the effect of drain extension with LAD doping and its variation on ambipolarity as well as also present the impact of LAD doping effect on DG-TFET performance. Apart from this, the analog/RFfigure of merit and delay analysis are also performed for drain extension length variation (Lextd) and compared with DG-FET behavior. Finally, we have demonstrated the influence of gate-drain underlap (UL), and different dielectric material for spacer and gate oxide on DG-TFET and its analog/RF performance for low power application. Here it is found that the drive current behaviour in DG-TFET with UL feature while using a different dielectric material for spacer is different in comparison to that of DG-FET. Further, the UL based hetro gate DG-TFET with low-k spacer (LK HGDG-TFET) is more resistive for drain induced barrier lowering (DIBL) as compared to DG-TFET with low-k spacer (LK DG-TFET). Our results also suggest that LK HGDG-TFET with gate-drain UL feature can be potential candidate for RF use. This investigation, which is made by numerical simulation, would be beneficial for a new generation of RF circuits and systems in a broad range of applications and operating frequencies covering RF spectrum. In addition, the results can be useful to other researchers for the development of robust compact models for analog/RF parameters. In a developing field where experimental results are still limited, these simulations can even be essential, since they allow the variation of a large number of parameters in a short amount of time. In this way, the work presented here can further our understanding of this emerging device, and can contribute to the progress made in future Tunnel FET fabrication and model development.