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Please use this identifier to cite or link to this item: https://dspace.iiti.ac.in/handle/123456789/4945
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dc.contributor.authorRoy, Dipanjanen_US
dc.contributor.authorSengupta, Anirbanen_US
dc.date.accessioned2022-03-17T01:00:00Z-
dc.date.accessioned2022-03-17T15:36:09Z-
dc.date.available2022-03-17T01:00:00Z-
dc.date.available2022-03-17T15:36:09Z-
dc.date.issued2018-
dc.identifier.citationRoy, D., Sarkar, P., Sengupta, A., & Naskar, M. K. (2018). Optimizing DSP cores using design transformation [hardware matters]. IEEE Consumer Electronics Magazine, 7(4), 91-94. doi:10.1109/MCE.2018.2816207en_US
dc.identifier.issn2162-2248-
dc.identifier.otherEID(2-s2.0-85048771703)-
dc.identifier.urihttps://doi.org/10.1109/MCE.2018.2816207-
dc.identifier.urihttps://dspace.iiti.ac.in/handle/123456789/4945-
dc.description.abstractReusable digital signal processing (DSP) intellectual property (IP) cores play a crucial role in numerous domains, including consumer electronics. However, optimizing DSP cores is crucial for the reduction of design area, delay, power, and so forth [1], [2]. Though several optimization techniques using evolutionary algorithms have been proposed, they incur design overhead and exploration time [1], [2]. © 2012 IEEE.en_US
dc.language.isoenen_US
dc.publisherInstitute of Electrical and Electronics Engineers Inc.en_US
dc.sourceIEEE Consumer Electronics Magazineen_US
dc.subjectElectronics engineeringen_US
dc.subjectElectronics industryen_US
dc.subjectDigital signal processing (DSP)en_US
dc.subjectDSP coreen_US
dc.subjectOptimization techniquesen_US
dc.subjectDigital signal processingen_US
dc.titleOptimizing DSP Cores Using Design Transformation [Hardware Matters]en_US
dc.typeJournal Articleen_US
Appears in Collections:Department of Computer Science and Engineering

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