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Please use this identifier to cite or link to this item: https://dspace.iiti.ac.in/handle/123456789/4949
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dc.contributor.authorSengupta, Anirbanen_US
dc.contributor.authorKachave, Deepaken_US
dc.date.accessioned2022-03-17T01:00:00Z-
dc.date.accessioned2022-03-17T15:36:10Z-
dc.date.available2022-03-17T01:00:00Z-
dc.date.available2022-03-17T15:36:10Z-
dc.date.issued2018-
dc.identifier.citationSengupta, A., & Kachave, D. (2018). Spatial and temporal redundancy for transient fault-tolerant datapath. IEEE Transactions on Aerospace and Electronic Systems, 54(3), 1168-1183. doi:10.1109/TAES.2017.2776038en_US
dc.identifier.issn0018-9251-
dc.identifier.otherEID(2-s2.0-85035751903)-
dc.identifier.urihttps://doi.org/10.1109/TAES.2017.2776038-
dc.identifier.urihttps://dspace.iiti.ac.in/handle/123456789/4949-
dc.description.abstractIn application specific integrated circuits used in aircraft control systems the effects of transient fault, both in temporal and spatial domain emanating from a single particle strike, cannot be ignored anymore. This is due to scaling of device geometry and surge in frequency. This paper presents novel fault-tolerant high-level synthesis methodology against temporal and spatial impacts of transient at reduced design cost (avg. ∼ 25%) and power (avg. ∼ 48%) than a recent approach. © 1965-2011 IEEE.en_US
dc.language.isoenen_US
dc.publisherInstitute of Electrical and Electronics Engineers Inc.en_US
dc.sourceIEEE Transactions on Aerospace and Electronic Systemsen_US
dc.subjectAircraft accidentsen_US
dc.subjectAircraft controlen_US
dc.subjectComputer hardwareen_US
dc.subjectCost benefit analysisen_US
dc.subjectFault toleranceen_US
dc.subjectFlight control systemsen_US
dc.subjectHigh level synthesisen_US
dc.subjectCircuit faultsen_US
dc.subjectFault tolerant systemsen_US
dc.subjectLow-cost designen_US
dc.subjectResilienceen_US
dc.subjectTransient faultsen_US
dc.subjectTransient analysisen_US
dc.titleSpatial and Temporal Redundancy for Transient Fault-Tolerant Datapathen_US
dc.typeJournal Articleen_US
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