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Please use this identifier to cite or link to this item: https://dspace.iiti.ac.in/handle/123456789/5152
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dc.contributor.authorNavlakha, Nupuren_US
dc.contributor.authorKranti, Abhinaven_US
dc.date.accessioned2022-03-17T01:00:00Z-
dc.date.accessioned2022-03-17T15:38:48Z-
dc.date.available2022-03-17T01:00:00Z-
dc.date.available2022-03-17T15:38:48Z-
dc.date.issued2019-
dc.identifier.citationNavlakha, N., Ansari, M. H. R., & Kranti, A. (2019). TFET based 1T-DRAM: Physics, significance and trade-offs. Paper presented at the 2019 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2019, doi:10.1109/S3S46989.2019.9320697en_US
dc.identifier.isbn9781728135236-
dc.identifier.otherEID(2-s2.0-85100845107)-
dc.identifier.urihttps://doi.org/10.1109/S3S46989.2019.9320697-
dc.identifier.urihttps://dspace.iiti.ac.in/handle/123456789/5152-
dc.description.abstractThe work showcases device physics, the significance and trade-offs of DRAM metrics in a Tunnel Field Effect Transistor (TFET) based 1T dynamic memory. The analysis shows physical phenomenon that governs speed, Power (P), Energy (E), density, Sense Margin (SM), Current Ratio (CR), Retention Time (RT) and Delay (D) of DRAM. The optimal use of biases and device parameters for application specific design results into low values of Write Time (TW = ∼0.5 ns), Read Time (TR = ∼10 ns) at read bias of 0.8 V with write power (PW) of ∼0.1 pW and high RT (∼1.9 s at 85 °C) at sub-100 nm gate lengths. © 2019 IEEE.en_US
dc.language.isoenen_US
dc.publisherInstitute of Electrical and Electronics Engineers Inc.en_US
dc.source2019 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2019en_US
dc.subjectCommerceen_US
dc.subjectEconomic and social effectsen_US
dc.subjectMicroelectronicsen_US
dc.subjectTunnel field effect transistorsen_US
dc.subjectApplication specificen_US
dc.subjectCurrent ratiosen_US
dc.subjectDevice parametersen_US
dc.subjectDevice physicsen_US
dc.subjectDynamic memoryen_US
dc.subjectPhysical phenomenaen_US
dc.subjectRetention timeen_US
dc.subjectTunnel field-effect transistors (TFET)en_US
dc.subjectDynamic random access storageen_US
dc.titleTFET based 1T-DRAM: Physics, Significance and Trade-offsen_US
dc.typeConference Paperen_US
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