Please use this identifier to cite or link to this item: https://dspace.iiti.ac.in/handle/123456789/5152
Title: TFET based 1T-DRAM: Physics, Significance and Trade-offs
Authors: Navlakha, Nupur
Kranti, Abhinav
Keywords: Commerce;Economic and social effects;Microelectronics;Tunnel field effect transistors;Application specific;Current ratios;Device parameters;Device physics;Dynamic memory;Physical phenomena;Retention time;Tunnel field-effect transistors (TFET);Dynamic random access storage
Issue Date: 2019
Publisher: Institute of Electrical and Electronics Engineers Inc.
Citation: Navlakha, N., Ansari, M. H. R., & Kranti, A. (2019). TFET based 1T-DRAM: Physics, significance and trade-offs. Paper presented at the 2019 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2019, doi:10.1109/S3S46989.2019.9320697
Abstract: The work showcases device physics, the significance and trade-offs of DRAM metrics in a Tunnel Field Effect Transistor (TFET) based 1T dynamic memory. The analysis shows physical phenomenon that governs speed, Power (P), Energy (E), density, Sense Margin (SM), Current Ratio (CR), Retention Time (RT) and Delay (D) of DRAM. The optimal use of biases and device parameters for application specific design results into low values of Write Time (TW = ∼0.5 ns), Read Time (TR = ∼10 ns) at read bias of 0.8 V with write power (PW) of ∼0.1 pW and high RT (∼1.9 s at 85 °C) at sub-100 nm gate lengths. © 2019 IEEE.
URI: https://doi.org/10.1109/S3S46989.2019.9320697
https://dspace.iiti.ac.in/handle/123456789/5152
ISBN: 9781728135236
Type of Material: Conference Paper
Appears in Collections:Department of Electrical Engineering

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