FPGA based architecture of video compression standard for space applications

Abstract

Compression is a main technique to reduce the bandwidth requirement for space applications as well as to reduce the storage requirement for data. Mass, volume and power are the most important parameters for space applications. Therefore, compression is the most efficient way to control all these parameters. Indian space research organization (ISRO) uses consultative committee for space data system (CCSDS) based image compression standard for the image data as well as video data. But CCSDS standard is not able to fulfill the requirement of high compression ratio. Therefore, ISRO planned to implement a real-time video compression standard for space applications. ISRO decided to implement the H.264 video compression standard with baseline profile for space applications. This standard fulfills the requirement of high compression standards with good quality of video. The video has 512 × 512 frame size for space applications. This algorithm can be used to implement the video compression for 512 × 512 resolution video and 352 × 288 resolution video. Field programmable gate array (FPGA) based design is selected to implement this standard. The complete implementation of this standard within a single FPGA is required to avoid the frequency and power issues. Xilinx and Microsemi are only two companies, which provide space graded and radiation hardened FPGAs with very limited series. This project is targeted on the Virtex 5Q - xq5vfx130t FPGA. This project is placed and routed on this FPGA successfully. It uses 88% of total slices of FPGA and 64% of total block random access memory (RAM) of FPGA. It can work up to 60 MHz input frequency. The basic H.264 algorithm and hardware implementation are explained within this thesis. Simulation waveforms, the compression ratio and the peak signal to noise ratio (PSNR) are discussed in this thesis.