Please use this identifier to cite or link to this item: https://dspace.iiti.ac.in/handle/123456789/5213
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dc.contributor.authorYeh, Chihtingen_US
dc.contributor.authorKranti, Abhinaven_US
dc.date.accessioned2022-03-17T01:00:00Z-
dc.date.accessioned2022-03-17T15:38:59Z-
dc.date.available2022-03-17T01:00:00Z-
dc.date.available2022-03-17T15:38:59Z-
dc.date.issued2018-
dc.identifier.citationKuo, C. -., Lin, J. -., Yeh, C. -., & Kranti, A. (2018). Characterization of double-gate PN type tunneling field-effect transistor. Paper presented at the 2018 14th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2018 - Proceedings, doi:10.1109/ICSICT.2018.8565713en_US
dc.identifier.isbn9781538644409-
dc.identifier.otherEID(2-s2.0-85060299277)-
dc.identifier.urihttps://doi.org/10.1109/ICSICT.2018.8565713-
dc.identifier.urihttps://dspace.iiti.ac.in/handle/123456789/5213-
dc.description.abstractIn this paper, we proposed an new Double-Gate (DG) PN-type tunneling field-effect transistor with exploiting induced channel layer (iTFETs) for line tunneling and low power applications (V D = 0.1V 0.05V). Unlike conventional TFET, with same type of doping in source and underneath the gate change the topology from PIN to PN TFET. We replace point tunneling with line tunneling, which can improves currents, average and minimum subthreshold swing. By using PN structure, the ambipolar effect can be effectively suppressed. Furthermore, the proposed topology improves the double and vertical gate results. These devices achieve 4.1 × 10 -7 A/μm of ON current (I ON (I d @ V G = V D ), 2.1 × 10 -17 A/μm of OFF current (I OFF (I d @ V G = 0 V), and 1.95 × 10 10 of ON/OFF current ratio (I ON /I OFF ). A minimum subthreshold swing SS avg = 12.2 mV/dec and the SS min = 5 mV/dec are obtained. © 2018 IEEE.en_US
dc.language.isoenen_US
dc.publisherInstitute of Electrical and Electronics Engineers Inc.en_US
dc.source2018 14th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2018 - Proceedingsen_US
dc.subjectIntegrated circuitsen_US
dc.subjectTopologyen_US
dc.subjectChannel layersen_US
dc.subjectDouble gateen_US
dc.subjectLow power applicationen_US
dc.subjectOn currentsen_US
dc.subjectON/OFF current ratioen_US
dc.subjectP-n structureen_US
dc.subjectSubthreshold swingen_US
dc.subjectTunneling field-effect transistorsen_US
dc.subjectTunnel field effect transistorsen_US
dc.titleCharacterization of Double-Gate PN Type Tunneling Field-Effect Transistoren_US
dc.typeConference Paperen_US
Appears in Collections:Department of Electrical Engineering

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