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https://dspace.iiti.ac.in/handle/123456789/5213
Title: | Characterization of Double-Gate PN Type Tunneling Field-Effect Transistor |
Authors: | Yeh, Chihting Kranti, Abhinav |
Keywords: | Integrated circuits;Topology;Channel layers;Double gate;Low power application;On currents;ON/OFF current ratio;P-n structure;Subthreshold swing;Tunneling field-effect transistors;Tunnel field effect transistors |
Issue Date: | 2018 |
Publisher: | Institute of Electrical and Electronics Engineers Inc. |
Citation: | Kuo, C. -., Lin, J. -., Yeh, C. -., & Kranti, A. (2018). Characterization of double-gate PN type tunneling field-effect transistor. Paper presented at the 2018 14th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2018 - Proceedings, doi:10.1109/ICSICT.2018.8565713 |
Abstract: | In this paper, we proposed an new Double-Gate (DG) PN-type tunneling field-effect transistor with exploiting induced channel layer (iTFETs) for line tunneling and low power applications (V D = 0.1V 0.05V). Unlike conventional TFET, with same type of doping in source and underneath the gate change the topology from PIN to PN TFET. We replace point tunneling with line tunneling, which can improves currents, average and minimum subthreshold swing. By using PN structure, the ambipolar effect can be effectively suppressed. Furthermore, the proposed topology improves the double and vertical gate results. These devices achieve 4.1 × 10 -7 A/μm of ON current (I ON (I d @ V G = V D ), 2.1 × 10 -17 A/μm of OFF current (I OFF (I d @ V G = 0 V), and 1.95 × 10 10 of ON/OFF current ratio (I ON /I OFF ). A minimum subthreshold swing SS avg = 12.2 mV/dec and the SS min = 5 mV/dec are obtained. © 2018 IEEE. |
URI: | https://doi.org/10.1109/ICSICT.2018.8565713 https://dspace.iiti.ac.in/handle/123456789/5213 |
ISBN: | 9781538644409 |
Type of Material: | Conference Paper |
Appears in Collections: | Department of Electrical Engineering |
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