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Please use this identifier to cite or link to this item: https://dspace.iiti.ac.in/handle/123456789/5218
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dc.contributor.authorNavlakha, Nupuren_US
dc.contributor.authorKranti, Abhinaven_US
dc.date.accessioned2022-03-17T01:00:00Z-
dc.date.accessioned2022-03-17T15:39:00Z-
dc.date.available2022-03-17T01:00:00Z-
dc.date.available2022-03-17T15:39:00Z-
dc.date.issued2018-
dc.identifier.citationNavlakha, N., & Kranti, A. (2018). Physical insights on junction controllability for improved performance of planar trigate tunnel FET as capacitorless dynamic memory. Paper presented at the International Conference on Simulation of Semiconductor Processes and Devices, SISPAD, , 2018-September 129-132. doi:10.1109/SISPAD.2018.8551717en_US
dc.identifier.isbn9781538667880-
dc.identifier.otherEID(2-s2.0-85059759740)-
dc.identifier.urihttps://doi.org/10.1109/SISPAD.2018.8551717-
dc.identifier.urihttps://dspace.iiti.ac.in/handle/123456789/5218-
dc.description.abstractThe work presents physical insights on the control of energy barriers at junctions of a planar trigate Tunnel FET (TFET) for dynamic memory applications. Results demonstrate the significance of electric field (EF) at each junction i.e. Source-Gate1 (S-G1), Drain-Gate2 (D-G2), and that between gates, evaluated through the energy barrier between G1-G2 (E b ) to improve Sense Margin (SM), Current Ratio (CR), speed (write time) and Retention Time (RT). The work highlights the impact of device parameters that aid to improve the performance metrics, and also reduce the associated trade-offs in dynamic memory. © 2018 IEEE.en_US
dc.language.isoenen_US
dc.publisherInstitute of Electrical and Electronics Engineers Inc.en_US
dc.sourceInternational Conference on Simulation of Semiconductor Processes and Devices, SISPADen_US
dc.subjectDrain currenten_US
dc.subjectDynamic random access storageen_US
dc.subjectEconomic and social effectsen_US
dc.subjectElectric fieldsen_US
dc.subjectEnergy barriersen_US
dc.subjectSemiconductor junctionsen_US
dc.subjectTunnel field effect transistorsen_US
dc.subjectTunnel junctionsen_US
dc.subjectCapacitor-lessen_US
dc.subjectControl of energiesen_US
dc.subjectCurrent ratiosen_US
dc.subjectDevice parametersen_US
dc.subjectJunctionen_US
dc.subjectPerformance metricsen_US
dc.subjectTrigateen_US
dc.subjectTunnel FET (TFET)en_US
dc.subjectDynamicsen_US
dc.titlePhysical Insights on Junction Controllability for Improved Performance of Planar Trigate Tunnel FET as Capacitorless Dynamic Memoryen_US
dc.typeConference Paperen_US
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