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https://dspace.iiti.ac.in/handle/123456789/5309
| Title: | Twin gate Tunnel FET based capacitorless dynamic memory |
| Authors: | Navlakha, Nupur Kranti, Abhinav |
| Keywords: | VLSI circuits;Band to band tunneling;Capacitor-less;Charge storage;Design and optimization;Mechanism-based;Reliable operation;Retention time;Tunnel field effect transistor;Field effect transistors |
| Issue Date: | 2017 |
| Publisher: | Institute of Electrical and Electronics Engineers Inc. |
| Citation: | Navlakha, N., Lin, J. -., & Kranti, A. (2017). Twin gate tunnel FET based capacitorless dynamic memory. Paper presented at the 2017 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2017, doi:10.1109/VLSI-TSA.2017.7942458 |
| Abstract: | The work presents insights into operation, design and optimization of twin gate Tunnel Field Effect Transistor (TFET) for dynamic memory. The architecture utilizes two front gates, with the first gate aligned to source and responsible for read mechanism based on Band-to-Band Tunneling (BTBT), while the second gate regulates the creation and maintenance of dedicated volume for charge storage. The twin gate based dynamic memory at optimized bias values exhibits enhanced retention time of 370 ms at 85 °C and 1.3 s at 27 °C for gate lengths of 100 nm with better scalability, reliable operation at higher temperatures, and reduced write time of 5 ns. © 2017 IEEE. |
| URI: | https://doi.org/10.1109/VLSI-TSA.2017.7942458 https://dspace.iiti.ac.in/handle/123456789/5309 |
| ISBN: | 9781509058051 |
| Type of Material: | Conference Paper |
| Appears in Collections: | Department of Electrical Engineering |
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