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https://dspace.iiti.ac.in/handle/123456789/5343
| Title: | Junctionless composite transistor for Ultra Low Power applications |
| Authors: | Kumar, Anand Kranti, Abhinav |
| Keywords: | Leakage currents;Nanoelectronics;Composite transistors;Elevated temperature;inverter;junctionless;Junctionless transistors;Noise margins;Ultra low power;Ultralow power application;Transistors |
| Issue Date: | 2016 |
| Publisher: | Institute of Electrical and Electronics Engineers Inc. |
| Citation: | Kumar, A., Parihar, M. S., & Kranti, A. (2016). Junctionless composite transistor for ultra low power applications. Paper presented at the 2014 IEEE International Nanoelectronics Conference, INEC 2014, doi:10.1109/INEC.2014.7460447 |
| Abstract: | In this work, we investigate the behavior of an Ultra Low Power (ULP) composite transistor in conventional inversion mode (INV) and junctionless (JL) topologies. JL ULP transistor shows enhanced on-to-off current ratio and lower leakage current at elevated temperatures. JL ULP inverter designed with composite transistor shows enhanced noise margin. The work demonstrates new opportunities for realizing future ULP circuits with junctionless transistor. © 2014 IEEE. |
| URI: | https://doi.org/10.1109/INEC.2014.7460447 https://dspace.iiti.ac.in/handle/123456789/5343 |
| ISBN: | 9781479950379 |
| Type of Material: | Conference Paper |
| Appears in Collections: | Department of Electrical Engineering |
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