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Please use this identifier to cite or link to this item: https://dspace.iiti.ac.in/handle/123456789/5358
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dc.contributor.authorKranti, Abhinaven_US
dc.date.accessioned2022-03-17T01:00:00Z-
dc.date.accessioned2022-03-17T15:41:40Z-
dc.date.available2022-03-17T01:00:00Z-
dc.date.available2022-03-17T15:41:40Z-
dc.date.issued2015-
dc.identifier.citationParihar, M. S., Liu, F. Y., Navarro, C., Barraud, S., Bawedin, M., Ionica, I., . . . Cristoloveanu, S. (2015). Back-gate effects and detailed characterization of junctionless transistor. Paper presented at the European Solid-State Device Research Conference, , 2015-November 282-285. doi:10.1109/ESSDERC.2015.7324769en_US
dc.identifier.isbn9781467371339-
dc.identifier.issn1930-8876-
dc.identifier.otherEID(2-s2.0-84959325496)-
dc.identifier.urihttps://doi.org/10.1109/ESSDERC.2015.7324769-
dc.identifier.urihttps://dspace.iiti.ac.in/handle/123456789/5358-
dc.description.abstractThe work addresses effect of inter-gate coupling on back-channel characteristics of planar accumulation-mode junctionless (JL) MOSFETs, fabricated with advanced FDSOI technology. A systematic methodology to extract and discriminate the contributions of bulk and accumulation-mode mobility has been developed. Front-gate voltage strongly controls the properties of back channel in ultra-thin heavily doped JL devices. It has been demonstrated that both volume and accumulation-mode mobilities increase when the front surface is in accumulation. © 2015 IEEE.en_US
dc.language.isoenen_US
dc.publisherEditions Frontieresen_US
dc.sourceEuropean Solid-State Device Research Conferenceen_US
dc.subjectCarrier mobilityen_US
dc.subjectCouplingsen_US
dc.subjectReconfigurable hardwareen_US
dc.subjectSolid state devicesen_US
dc.subjectAccumulation modesen_US
dc.subjectBack channelsen_US
dc.subjectBack gate effectsen_US
dc.subjectHeavily dopeden_US
dc.subjectjunctionlessen_US
dc.subjectJunctionless transistorsen_US
dc.subjectSOI-MOSFETsen_US
dc.subjectSystematic methodologyen_US
dc.subjectMOSFET devicesen_US
dc.titleBack-gate effects and detailed characterization of junctionless transistoren_US
dc.typeConference Paperen_US
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