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DC Field | Value | Language |
---|---|---|
dc.contributor.author | Vishvakarma, Santosh Kumar | en_US |
dc.date.accessioned | 2022-03-17T01:00:00Z | - |
dc.date.accessioned | 2022-03-17T15:41:42Z | - |
dc.date.available | 2022-03-17T01:00:00Z | - |
dc.date.available | 2022-03-17T15:41:42Z | - |
dc.date.issued | 2015 | - |
dc.identifier.citation | Bhatia, P., Reniwal, B. S., & Vishvakarma, S. K. (2015). An offset-tolerant self-correcting sense amplifier for robust high speed SRAM. Paper presented at the 19th International Symposium on VLSI Design and Test, VDAT 2015 - Proceedings, doi:10.1109/ISVDAT.2015.7208082 | en_US |
dc.identifier.isbn | 9781479917433 | - |
dc.identifier.other | EID(2-s2.0-84961221130) | - |
dc.identifier.uri | https://doi.org/10.1109/ISVDAT.2015.7208082 | - |
dc.identifier.uri | https://dspace.iiti.ac.in/handle/123456789/5365 | - |
dc.description.abstract | In this paper we have proposed a novel Sense Amplifier (SA) design which is capable of predetermining the direction of offset in threshold voltage in the sensing transistors and which provides up to 24% more current differential by activating a path for current to flow in a device, parallel to the weaker transistor, thus compensating the inherent offset. Due to its self correcting capability, the design is called a Self Correcting Sense Amplifier (SCSA). Analysis carried out on Current Latch Sense Amplifier (CLSA) and SCSA showed 2.3x offset tolerance in SCSA when compared to CLSA at high-density SRAM conditions (500fF bit-line capacitance). SCSA also consumed 9% less dynamic power and offers 13% less sensing delay in offset condition. This resulted in a 27% reduction in power delay product. It thus offers a much better read-effectiveness and robustness against device mismatch and bit-line capacitances as well as VDD variation. © 2015 IEEE. | en_US |
dc.language.iso | en | en_US |
dc.publisher | Institute of Electrical and Electronics Engineers Inc. | en_US |
dc.source | 19th International Symposium on VLSI Design and Test, VDAT 2015 - Proceedings | en_US |
dc.subject | Capacitance | en_US |
dc.subject | Design | en_US |
dc.subject | Integrated circuit design | en_US |
dc.subject | Static random access storage | en_US |
dc.subject | Threshold voltage | en_US |
dc.subject | Bitline capacitance | en_US |
dc.subject | Current differential | en_US |
dc.subject | High density SRAM | en_US |
dc.subject | inter die variations | en_US |
dc.subject | intra die variations | en_US |
dc.subject | Latch sense amplifiers | en_US |
dc.subject | Offset | en_US |
dc.subject | Power delay product | en_US |
dc.subject | Amplifiers (electronic) | en_US |
dc.title | An offset-tolerant self-correcting sense amplifier for robust high speed SRAM | en_US |
dc.type | Conference Paper | en_US |
Appears in Collections: | Department of Electrical Engineering |
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