Please use this identifier to cite or link to this item: https://dspace.iiti.ac.in/handle/123456789/5365
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dc.contributor.authorVishvakarma, Santosh Kumaren_US
dc.date.accessioned2022-03-17T01:00:00Z-
dc.date.accessioned2022-03-17T15:41:42Z-
dc.date.available2022-03-17T01:00:00Z-
dc.date.available2022-03-17T15:41:42Z-
dc.date.issued2015-
dc.identifier.citationBhatia, P., Reniwal, B. S., & Vishvakarma, S. K. (2015). An offset-tolerant self-correcting sense amplifier for robust high speed SRAM. Paper presented at the 19th International Symposium on VLSI Design and Test, VDAT 2015 - Proceedings, doi:10.1109/ISVDAT.2015.7208082en_US
dc.identifier.isbn9781479917433-
dc.identifier.otherEID(2-s2.0-84961221130)-
dc.identifier.urihttps://doi.org/10.1109/ISVDAT.2015.7208082-
dc.identifier.urihttps://dspace.iiti.ac.in/handle/123456789/5365-
dc.description.abstractIn this paper we have proposed a novel Sense Amplifier (SA) design which is capable of predetermining the direction of offset in threshold voltage in the sensing transistors and which provides up to 24% more current differential by activating a path for current to flow in a device, parallel to the weaker transistor, thus compensating the inherent offset. Due to its self correcting capability, the design is called a Self Correcting Sense Amplifier (SCSA). Analysis carried out on Current Latch Sense Amplifier (CLSA) and SCSA showed 2.3x offset tolerance in SCSA when compared to CLSA at high-density SRAM conditions (500fF bit-line capacitance). SCSA also consumed 9% less dynamic power and offers 13% less sensing delay in offset condition. This resulted in a 27% reduction in power delay product. It thus offers a much better read-effectiveness and robustness against device mismatch and bit-line capacitances as well as VDD variation. © 2015 IEEE.en_US
dc.language.isoenen_US
dc.publisherInstitute of Electrical and Electronics Engineers Inc.en_US
dc.source19th International Symposium on VLSI Design and Test, VDAT 2015 - Proceedingsen_US
dc.subjectCapacitanceen_US
dc.subjectDesignen_US
dc.subjectIntegrated circuit designen_US
dc.subjectStatic random access storageen_US
dc.subjectThreshold voltageen_US
dc.subjectBitline capacitanceen_US
dc.subjectCurrent differentialen_US
dc.subjectHigh density SRAMen_US
dc.subjectinter die variationsen_US
dc.subjectintra die variationsen_US
dc.subjectLatch sense amplifiersen_US
dc.subjectOffseten_US
dc.subjectPower delay producten_US
dc.subjectAmplifiers (electronic)en_US
dc.titleAn offset-tolerant self-correcting sense amplifier for robust high speed SRAMen_US
dc.typeConference Paperen_US
Appears in Collections:Department of Electrical Engineering

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