Please use this identifier to cite or link to this item: https://dspace.iiti.ac.in/handle/123456789/5365
Title: An offset-tolerant self-correcting sense amplifier for robust high speed SRAM
Authors: Vishvakarma, Santosh Kumar
Keywords: Capacitance;Design;Integrated circuit design;Static random access storage;Threshold voltage;Bitline capacitance;Current differential;High density SRAM;inter die variations;intra die variations;Latch sense amplifiers;Offset;Power delay product;Amplifiers (electronic)
Issue Date: 2015
Publisher: Institute of Electrical and Electronics Engineers Inc.
Citation: Bhatia, P., Reniwal, B. S., & Vishvakarma, S. K. (2015). An offset-tolerant self-correcting sense amplifier for robust high speed SRAM. Paper presented at the 19th International Symposium on VLSI Design and Test, VDAT 2015 - Proceedings, doi:10.1109/ISVDAT.2015.7208082
Abstract: In this paper we have proposed a novel Sense Amplifier (SA) design which is capable of predetermining the direction of offset in threshold voltage in the sensing transistors and which provides up to 24% more current differential by activating a path for current to flow in a device, parallel to the weaker transistor, thus compensating the inherent offset. Due to its self correcting capability, the design is called a Self Correcting Sense Amplifier (SCSA). Analysis carried out on Current Latch Sense Amplifier (CLSA) and SCSA showed 2.3x offset tolerance in SCSA when compared to CLSA at high-density SRAM conditions (500fF bit-line capacitance). SCSA also consumed 9% less dynamic power and offers 13% less sensing delay in offset condition. This resulted in a 27% reduction in power delay product. It thus offers a much better read-effectiveness and robustness against device mismatch and bit-line capacitances as well as VDD variation. © 2015 IEEE.
URI: https://doi.org/10.1109/ISVDAT.2015.7208082
https://dspace.iiti.ac.in/handle/123456789/5365
ISBN: 9781479917433
Type of Material: Conference Paper
Appears in Collections:Department of Electrical Engineering

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