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Please use this identifier to cite or link to this item: https://dspace.iiti.ac.in/handle/123456789/5421
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dc.contributor.authorKranti, Abhinaven_US
dc.date.accessioned2022-03-17T01:00:00Z-
dc.date.accessioned2022-03-17T15:41:55Z-
dc.date.available2022-03-17T01:00:00Z-
dc.date.available2022-03-17T15:41:55Z-
dc.date.issued2013-
dc.identifier.citationGhosh, D., Parihar, M. S., & Kranti, A. (2013). Optimizing nanoscale MOSFET architecture for low power analog/RF applications. Paper presented at the Proceedings - Winter Simulation Conference, 22-23. doi:10.1109/INEC.2013.6465941en_US
dc.identifier.isbn9781467348416-
dc.identifier.issn0891-7736-
dc.identifier.otherEID(2-s2.0-84874774225)-
dc.identifier.urihttps://doi.org/10.1109/INEC.2013.6465941-
dc.identifier.urihttps://dspace.iiti.ac.in/handle/123456789/5421-
dc.description.abstractThis work reports on possible ways of improving analog/RF performance metrics, through device structure optimization, for low power applications. It is shown that underlap source/drain (S/D) design and junctionless transistor architecture can both yield improved analog/RF figures of merit in comparison to conventional abrupt source/drain MOSFETs. Junctionless devices overcome the gain-bandwidth trade-off associated with analog design. The results are significant for RFICs in emerging ultra-low-power technologies. © 2013 IEEE.en_US
dc.language.isoenen_US
dc.sourceProceedings - Winter Simulation Conferenceen_US
dc.subjectAnalog designen_US
dc.subjectAnalog/RF performanceen_US
dc.subjectDevice structure optimizationen_US
dc.subjectDouble gate MOSFETen_US
dc.subjectFigures of meritsen_US
dc.subjectGain bandwidthen_US
dc.subjectJunctionlessen_US
dc.subjectJunctionless devicesen_US
dc.subjectJunctionless transistorsen_US
dc.subjectLow Poweren_US
dc.subjectLow power applicationen_US
dc.subjectMOSFETsen_US
dc.subjectNanoscale MOSFETsen_US
dc.subjectUltra-low poweren_US
dc.subjectMOS devicesen_US
dc.subjectNanoelectronicsen_US
dc.subjectStructural optimizationen_US
dc.subjectMOSFET devicesen_US
dc.titleOptimizing nanoscale MOSFET architecture for low power analog/RF applicationsen_US
dc.typeConference Paperen_US
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