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| Title: | Optimizing nanoscale MOSFET architecture for low power analog/RF applications |
| Authors: | Kranti, Abhinav |
| Keywords: | Analog design;Analog/RF performance;Device structure optimization;Double gate MOSFET;Figures of merits;Gain bandwidth;Junctionless;Junctionless devices;Junctionless transistors;Low Power;Low power application;MOSFETs;Nanoscale MOSFETs;Ultra-low power;MOS devices;Nanoelectronics;Structural optimization;MOSFET devices |
| Issue Date: | 2013 |
| Citation: | Ghosh, D., Parihar, M. S., & Kranti, A. (2013). Optimizing nanoscale MOSFET architecture for low power analog/RF applications. Paper presented at the Proceedings - Winter Simulation Conference, 22-23. doi:10.1109/INEC.2013.6465941 |
| Abstract: | This work reports on possible ways of improving analog/RF performance metrics, through device structure optimization, for low power applications. It is shown that underlap source/drain (S/D) design and junctionless transistor architecture can both yield improved analog/RF figures of merit in comparison to conventional abrupt source/drain MOSFETs. Junctionless devices overcome the gain-bandwidth trade-off associated with analog design. The results are significant for RFICs in emerging ultra-low-power technologies. © 2013 IEEE. |
| URI: | https://doi.org/10.1109/INEC.2013.6465941 https://dspace.iiti.ac.in/handle/123456789/5421 |
| ISBN: | 9781467348416 |
| ISSN: | 0891-7736 |
| Type of Material: | Conference Paper |
| Appears in Collections: | Department of Electrical Engineering |
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