Please use this identifier to cite or link to this item: https://dspace.iiti.ac.in/handle/123456789/5423
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dc.contributor.authorKranti, Abhinaven_US
dc.date.accessioned2022-03-17T01:00:00Z-
dc.date.accessioned2022-03-17T15:41:55Z-
dc.date.available2022-03-17T01:00:00Z-
dc.date.available2022-03-17T15:41:55Z-
dc.date.issued2013-
dc.identifier.citationParihar, M. S., Ghosh, D., Armstrong, G. A., & Kranti, A. (2013). Single transistor latch phenomena in junctionless nanotransistors. Paper presented at the Proceedings - Winter Simulation Conference, 72-73. doi:10.1109/INEC.2013.6465957en_US
dc.identifier.isbn9781467348416-
dc.identifier.issn0891-7736-
dc.identifier.otherEID(2-s2.0-84874761430)-
dc.identifier.urihttps://doi.org/10.1109/INEC.2013.6465957-
dc.identifier.urihttps://dspace.iiti.ac.in/handle/123456789/5423-
dc.description.abstractIn this work, we analyze the dependence of steep subthreshold (S-slope) on device and bias parameters of Junctionless (JL) MOSFETs. It is observed that for certain parameters and bias conditions, the JL transistor cannot be turned OFF resulting in a single transistor latch. This phenomenon is an extreme case of impact ionization in JL MOSFETs. It is shown that thicker values of silicon film thickness and gate oxide along with higher drain bias can drive the JL MOSFET in to the latch state. © 2013 IEEE.en_US
dc.language.isoenen_US
dc.sourceProceedings - Winter Simulation Conferenceen_US
dc.subjectBias conditionsen_US
dc.subjectBias parametersen_US
dc.subjectDrain biasen_US
dc.subjectGate oxideen_US
dc.subjectJunctionlessen_US
dc.subjectMOS-FETen_US
dc.subjectMOSFETsen_US
dc.subjectSilicon film thicknessen_US
dc.subjectSingle transistorsen_US
dc.subjectSubthresholden_US
dc.subjectImpact ionizationen_US
dc.subjectMOSFET devicesen_US
dc.subjectNanoelectronicsen_US
dc.subjectNanotransistorsen_US
dc.titleSingle transistor latch phenomena in Junctionless Nanotransistorsen_US
dc.typeConference Paperen_US
Appears in Collections:Department of Electrical Engineering

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