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https://dspace.iiti.ac.in/handle/123456789/5423
| Title: | Single transistor latch phenomena in Junctionless Nanotransistors |
| Authors: | Kranti, Abhinav |
| Keywords: | Bias conditions;Bias parameters;Drain bias;Gate oxide;Junctionless;MOS-FET;MOSFETs;Silicon film thickness;Single transistors;Subthreshold;Impact ionization;MOSFET devices;Nanoelectronics;Nanotransistors |
| Issue Date: | 2013 |
| Citation: | Parihar, M. S., Ghosh, D., Armstrong, G. A., & Kranti, A. (2013). Single transistor latch phenomena in junctionless nanotransistors. Paper presented at the Proceedings - Winter Simulation Conference, 72-73. doi:10.1109/INEC.2013.6465957 |
| Abstract: | In this work, we analyze the dependence of steep subthreshold (S-slope) on device and bias parameters of Junctionless (JL) MOSFETs. It is observed that for certain parameters and bias conditions, the JL transistor cannot be turned OFF resulting in a single transistor latch. This phenomenon is an extreme case of impact ionization in JL MOSFETs. It is shown that thicker values of silicon film thickness and gate oxide along with higher drain bias can drive the JL MOSFET in to the latch state. © 2013 IEEE. |
| URI: | https://doi.org/10.1109/INEC.2013.6465957 https://dspace.iiti.ac.in/handle/123456789/5423 |
| ISBN: | 9781467348416 |
| ISSN: | 0891-7736 |
| Type of Material: | Conference Paper |
| Appears in Collections: | Department of Electrical Engineering |
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