Please use this identifier to cite or link to this item: https://dspace.iiti.ac.in/handle/123456789/5444
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dc.contributor.authorKranti, Abhinaven_US
dc.date.accessioned2022-03-17T01:00:00Z-
dc.date.accessioned2022-03-17T15:42:01Z-
dc.date.available2022-03-17T01:00:00Z-
dc.date.available2022-03-17T15:42:01Z-
dc.date.issued2011-
dc.identifier.citationKranti, A., Raskin, J. -., & Armstrong, G. A. (2011). Source/drain engineered ultra low power analog/RF UTBB MOSFETs. Paper presented at the 2011 12th International Conference on Ultimate Integration on Silicon, ULIS 2011, 114-117. doi:10.1109/ULIS.2011.5757997en_US
dc.identifier.isbn9781457700903-
dc.identifier.otherEID(2-s2.0-79957981297)-
dc.identifier.urihttps://doi.org/10.1109/ULIS.2011.5757997-
dc.identifier.urihttps://dspace.iiti.ac.in/handle/123456789/5444-
dc.description.abstractWe present a novel optimization technique for ultra-low-power analog/RF Ultra Thin Body BOX (UTBB) MOSFETs. UTBB devices are optimized in bias range corresponding to peak of transconductance-to-current ratio (gm/I ds) and cut-off frequency (fT) product i.e. g mfT/Ids as it represents a sweet spot between speed and power. It is demonstrated that the use of underlap source/drain (S/D) architecture in UTBB devices improve gmfT/Ids, intrinsic voltage gain (AVO), cut-off frequency (fT) and linearity (VIP3) with downscaling. © 2011 IEEE.en_US
dc.language.isoenen_US
dc.source2011 12th International Conference on Ultimate Integration on Silicon, ULIS 2011en_US
dc.subjectCut-offen_US
dc.subjectDown-scalingen_US
dc.subjectMOSFETsen_US
dc.subjectOptimization techniquesen_US
dc.subjectSweet spoten_US
dc.subjectTransconductance-to-current ratioen_US
dc.subjectUltra-low poweren_US
dc.subjectUltra-thin-bodyen_US
dc.subjectVoltage gainen_US
dc.subjectOptimizationen_US
dc.subjectMOSFET devicesen_US
dc.titleSource/drain engineered ultra low power analog/RF UTBB MOSFETsen_US
dc.typeConference Paperen_US
Appears in Collections:Department of Electrical Engineering

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