High-performance radiation hardened NMOS only Schmitt Trigger based latch designs

Abstract

CMOS circuits based on scaled transistors are typically more susceptible to soft errors caused by energetic particles in the radiation environment than circuits employing their large-area counterparts. In this paper, a soft error tolerant latch built on a Schmitt trigger, which is entirely realized with NMOS transistors with an additional voltage booster, which we refer to as NST-VB, is proposed. To evaluate the circuits’ radiation resilience, we identify the most sensitive nodes by analyzing the critical charges at the various latches’ internal sensitive nodes. We also examine the linear energy transfer (LET) of the essential latches and observe that the NST-VB latch has an improved LET of 0.386MeVcm2/mg as compared to 0.231MeVcm2/mg and 0.365MeVcm2/mg for unhardened latch and ST latch, respectively. For the process variation analysis, we further examined 5k Monte Carlo simulations to analyze the impact of device variability on our design and observe that the proposed NST-VB latch has 1.96 × less variability critical voltage concerning the ST latch. Further, the logic flipping probability for NST-VB latch is 48.32% compared to 53.04% for ST latch. Also, the critical charge to power delay area product ratio (QPAR) is calculated and evaluated for the proposed latch’s effectiveness compared to other considered latches. © 2021, The Author(s), under exclusive licence to Springer Science+Business Media, LLC, part of Springer Nature.