Analysis of charge trap nand flash memory for improved reliability

Abstract

Hard disk drives (HDD) have immensely been used as external storage device in computer system for around half the century. However, HDDs are being lesser appealing these days due to its long read/write access latency, high power consumption and fragility. To provide the alternative method for external storage, ash memory was invented by Toshiba in 1980's. Flash Memories are more reliable and power e_cient than HDD which makes it more suitable for battery operated hand-hold devices such as smart phones, tablets, notebooks etc. Importantly, the ash memory cell stores the electrical charge in oating gate (FG) or charge trap (CT) layer. Further, categorisation of NAND and NOR ash memory depends on the circuit connections of ash memory cells. Here, NOR ash memory can provide fast random access hence shows its suitabil- ity for code storage. However, with NOR technology, larger cell size and di_culty to scale the ash cell size makes it less suitable for bulk data storage. On the other hand, smaller cell size with NAND technology allows bulk data storage with small cost per bit as compared to NOR technology for same die area. Therefore, now a days, NAND ash memory is used in majority of consumer applications such as digital video/music player, Flash drives, MP3 players, multi-function cell phones, digital cameras and USB drives etc for bulk data storage. The large application market of NAND ash memory makes it the most signi_cant non-volatile memory solution for the next decade.

Further, to satisfy its demand in handhold applications, the NAND ash memory must be able to provide high data storing capacity with low cost per bit. For the reali-sation of such cost e_ective and high density NAND ash memory, scaling of memory cell size is important. Owing to this scaling of cell size, high capacity NAND ash memory can be obtained on the same die area. In this regard, it has already been predicted that half pitch of the NAND ash memory cell in two dimensional (2D) in-tegration would be scaled below 10nm by 2025. These extremely scaled memory cells will impose several limitations on the performance of the ash memory such as short channel e_ects (SCEs) and reduced data retention etc. In fact, while scaling, a ash memory cell has been shown to be more prone to the SCE than any other logic device due to the requirement of thick gate oxide stack (Tunnel Oxide + FG/CT + Inter-Poly I Dielectric thickness). High thickness of oxide stack is required to achieve high data retention. However, small thickness of gate oxide stack is needed to have improved SCEs. This trade-o_ between SCEs and data retention presents bottleneck for future scaling of ash memory. Therefore, in this thesis, we explore a exible method that can improve SCEs as well as data retention without altering the gate oxide stack thickness. At the same time, by source/drain engineering, we show that junction boost leakage current can be reduced for CT ash memory cell with improved SCEs. Further, in this thesis, we investigate e_ect of lightly doped drain (LDD) depth variation on the relia-bility of CT based NAND ash Memory. Here, to monitor the reliability, we investigate residual charge in CT layer after erase operation and then its e_ect on the endurance performance of the ash memory cell.

In the same walk, to scale the NAND ash memory e_ciently with the reduced cost per bit, several three dimensional (3D) NAND ash memory structure have been pro- posed in the literature. Here, to obtain high density NAND ash memory on the same area, memory array is realised in the vertical direction. These 3D NAND ash memo- ries are faster in operation, has improved wear life and has lower bit error rate (BER) per KB of data than 2D ash. These 3D integration with NAND ash memory serves as the basic idea for the system known as Solid State Drives (SSD). A 3D structure can be implemented with two con_gurations i.e. Vertical Gate (VG) and Vertical Channel (VC) according to the direction of current ow. In this thesis, we use a single string of NAND ash memory cell having VG con_guration which seems more appealing in terms of pitch scaling, selection of channel material and degradation of read current with large number of stacking layers, as compared to the VC con_guration. In addi- tion, in this thesis, we explore junction-free architecture of NAND ash memory string. Further, this thesis analyses the e_ect of channel engineering method to improve the data retention-SCE tradeo_ in CT based VG junction-free NAND ash memory string without altering the gate oxide stack. Also, we explore the e_ect of VPASS voltage to other adjacent cells in NAND string. Above all, the theoretical _ndings in this thesis provide useful insights and guidelines for the design of reliable ash memory systems.