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DC Field | Value | Language |
---|---|---|
dc.contributor.author | Kranti, Abhinav | en_US |
dc.date.accessioned | 2022-03-17T01:00:00Z | - |
dc.date.accessioned | 2022-03-17T15:43:23Z | - |
dc.date.available | 2022-03-17T01:00:00Z | - |
dc.date.available | 2022-03-17T15:43:23Z | - |
dc.date.issued | 2019 | - |
dc.identifier.citation | Gupta, M., & Kranti, A. (2019). Bi-directional junctionless transistor for logic and memory applications. IEEE Transactions on Electron Devices, 66(10), 4446-4452. doi:10.1109/TED.2019.2934191 | en_US |
dc.identifier.issn | 0018-9383 | - |
dc.identifier.other | EID(2-s2.0-85077757666) | - |
dc.identifier.uri | https://doi.org/10.1109/TED.2019.2934191 | - |
dc.identifier.uri | https://dspace.iiti.ac.in/handle/123456789/5702 | - |
dc.description.abstract | This article reports on logic and memory functionality of vertically stacked bidirectional junctionless (BiJL) transistor, which can be operated as nMOS or pMOS depending on the biases applied. An inverter can be realized with a single BiJL transistor. If a complement of inputs is available, then NAND, NOR, and XOR logic can also be realized through a single BiJL transistor. The thickness of separation oxide between n-type and p-type films can be utilized to either achieve hysteresis or the absence of the same. Results provide insights into device physics, operation, and showcase new viewpoints for designing logic and memory devices with vertically stacked JL architecture, thus achieving the desired functionality with a lesser number of transistors. © 1963-2012 IEEE. | en_US |
dc.language.iso | en | en_US |
dc.publisher | Institute of Electrical and Electronics Engineers Inc. | en_US |
dc.source | IEEE Transactions on Electron Devices | en_US |
dc.subject | Impact ionization | en_US |
dc.subject | MOSFET devices | en_US |
dc.subject | Oxide films | en_US |
dc.subject | Static random access storage | en_US |
dc.subject | Transistors | en_US |
dc.subject | Bi-directional | en_US |
dc.subject | Bidirectional (Bi) | en_US |
dc.subject | Device physics | en_US |
dc.subject | Double gate | en_US |
dc.subject | junctionless (JL) | en_US |
dc.subject | Junctionless transistors | en_US |
dc.subject | Memory applications | en_US |
dc.subject | MOS-FET | en_US |
dc.subject | Computer circuits | en_US |
dc.title | Bi-Directional Junctionless Transistor for Logic and Memory Applications | en_US |
dc.type | Journal Article | en_US |
Appears in Collections: | Department of Electrical Engineering |
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