Please use this identifier to cite or link to this item: https://dspace.iiti.ac.in/handle/123456789/5842
Title: A Compact Electrical Modelling for Top-Gated Doped Graphene Field-Effect Transistor
Authors: Chauhan, Nitesh
Vishvakarma, Santosh Kumar
Keywords: Capacitance;Drain current;Electric field effects;Electric resistance;Field effect transistors;Frequency estimation;Graphene;Nanoelectronics;Nanotechnology;Threshold voltage;Transconductance;Channel materials;Device modeling;Digital circuit design;Graphene field-effect transistors;Graphene fieldeffect transistors (GFET);Intrinsic voltage gains;Threshold voltages (Vth);Transconductance efficiency;Graphene transistors
Issue Date: 2018
Publisher: Taylor and Francis Ltd
Citation: Upadhyay, A. K., Chauhan, N., & Vishvakarma, S. K. (2018). A compact electrical modelling for top-gated doped graphene field-effect transistor. IETE Journal of Research, 64(3), 317-323. doi:10.1080/03772063.2017.1355752
Abstract: In this paper, we have developed an inclusive model for top-gated doped graphene field-effect transistor (GFET). The proposed model is concise and accurate for calculations of the electrical parameters that are used in digital circuit design. The doping in single layer graphene sheet is one of the ways to create a bandgap as well as to introduce the threshold voltage (V TH) concept in GFET. Further, the modelled expressions are used for estimation of quantum capacitance (Cq), which is used for the modelling of drain current (ID), small-signal transconductance gain (gm), output resistance (ro), and figures of merit such as intrinsic voltage gain (AV), transconductance efficiency (gm/ID), and cut-off frequency (fT). © 2018, © 2018 IETE.
URI: https://doi.org/10.1080/03772063.2017.1355752
https://dspace.iiti.ac.in/handle/123456789/5842
ISSN: 0377-2063
Type of Material: Review
Appears in Collections:Department of Electrical Engineering

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