Analysis of trap-assisted tunnelling in asymmetrical underlap 3D-cylindrical GAA-TFET based on hetero-spacer engineering for improved device reliability

Abstract

A unique design for an asymmetrical underlap (AU) cylindrical-gate-all-around (GAA)-n-tunnel field effect transistor (TFET) based on heterospacer engineering with trap-assisted tunnelling (TAT) for reliability concern is proposed and validated. Here, DC and analogue performances such as ION, IOFF, SS, ION/IOFF, Cgs, and Cgd have been investigated, while included TAT model and compared the examined device with AU GAA-TFET based on homo-spacer (HS) dielectric. On the basis of observation, the proposed device increases ON current as high as 2.1 × 10-6 A/μm, which corresponds to 1024 times improvement in ION/IOFF when compared with device based on HS. It also suppresses ambipolar behaviour with fast switching ON-OFF transition due to low leakage current (IOFF). These performances are mainly produced due to AU and low-k spacer dielectric which is replaced by high-k dielectric over source side spacer of the device, whereas drain side spacer is placed with high-k material along with increase in series resistance across drain-channel junction caused by drain underlap. Low-k spacer reduces the fringing field, and the depletion does not form at the source-gate edge, hence high source-channel tunnelling junction. © The Institution of Engineering and Technology 2017.