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DC Field | Value | Language |
---|---|---|
dc.contributor.author | Kranti, Abhinav | en_US |
dc.date.accessioned | 2022-03-17T01:00:00Z | - |
dc.date.accessioned | 2022-03-17T15:45:34Z | - |
dc.date.available | 2022-03-17T01:00:00Z | - |
dc.date.available | 2022-03-17T15:45:34Z | - |
dc.date.issued | 2016 | - |
dc.identifier.citation | Parihar, M. S., Liu, F., Navarro, C., Barraud, S., Bawedin, M., Ionica, I., . . . Cristoloveanu, S. (2016). Back-gate effects and mobility characterization in junctionless transistor. Solid-State Electronics, 125, 154-160. doi:10.1016/j.sse.2016.07.016 | en_US |
dc.identifier.issn | 0038-1101 | - |
dc.identifier.other | EID(2-s2.0-84992761643) | - |
dc.identifier.uri | https://doi.org/10.1016/j.sse.2016.07.016 | - |
dc.identifier.uri | https://dspace.iiti.ac.in/handle/123456789/6011 | - |
dc.description.abstract | This work addresses the effect of inter-gate coupling on back-channel characteristics of planar accumulation-mode junctionless (JL) MOSFETs, fabricated with advanced Fully Depleted Silicon-on-Insulator (FDSOI) technology. A systematic methodology to extract and distinguish the contributions of bulk and accumulation-mode mobility has been developed. Front-gate voltage strongly controls the transport properties of back channel in ultra-thin heavily doped JL devices. It is demonstrated that both volume and accumulation-layer mobility values increase when the front interface is in accumulation. © 2016 Elsevier Ltd | en_US |
dc.language.iso | en | en_US |
dc.publisher | Elsevier Ltd | en_US |
dc.source | Solid-State Electronics | en_US |
dc.subject | Carrier mobility | en_US |
dc.subject | Couplings | en_US |
dc.subject | MOSFET devices | en_US |
dc.subject | Reconfigurable hardware | en_US |
dc.subject | Accumulation layers | en_US |
dc.subject | Accumulation modes | en_US |
dc.subject | Back channels | en_US |
dc.subject | Fully depleted silicon-on-insulator | en_US |
dc.subject | Junctionless | en_US |
dc.subject | Junctionless transistors | en_US |
dc.subject | SOI-MOSFETs | en_US |
dc.subject | Systematic methodology | en_US |
dc.subject | Silicon on insulator technology | en_US |
dc.title | Back-gate effects and mobility characterization in junctionless transistor | en_US |
dc.type | Journal Article | en_US |
Appears in Collections: | Department of Electrical Engineering |
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