Please use this identifier to cite or link to this item: https://dspace.iiti.ac.in/handle/123456789/6011
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dc.contributor.authorKranti, Abhinaven_US
dc.date.accessioned2022-03-17T01:00:00Z-
dc.date.accessioned2022-03-17T15:45:34Z-
dc.date.available2022-03-17T01:00:00Z-
dc.date.available2022-03-17T15:45:34Z-
dc.date.issued2016-
dc.identifier.citationParihar, M. S., Liu, F., Navarro, C., Barraud, S., Bawedin, M., Ionica, I., . . . Cristoloveanu, S. (2016). Back-gate effects and mobility characterization in junctionless transistor. Solid-State Electronics, 125, 154-160. doi:10.1016/j.sse.2016.07.016en_US
dc.identifier.issn0038-1101-
dc.identifier.otherEID(2-s2.0-84992761643)-
dc.identifier.urihttps://doi.org/10.1016/j.sse.2016.07.016-
dc.identifier.urihttps://dspace.iiti.ac.in/handle/123456789/6011-
dc.description.abstractThis work addresses the effect of inter-gate coupling on back-channel characteristics of planar accumulation-mode junctionless (JL) MOSFETs, fabricated with advanced Fully Depleted Silicon-on-Insulator (FDSOI) technology. A systematic methodology to extract and distinguish the contributions of bulk and accumulation-mode mobility has been developed. Front-gate voltage strongly controls the transport properties of back channel in ultra-thin heavily doped JL devices. It is demonstrated that both volume and accumulation-layer mobility values increase when the front interface is in accumulation. © 2016 Elsevier Ltden_US
dc.language.isoenen_US
dc.publisherElsevier Ltden_US
dc.sourceSolid-State Electronicsen_US
dc.subjectCarrier mobilityen_US
dc.subjectCouplingsen_US
dc.subjectMOSFET devicesen_US
dc.subjectReconfigurable hardwareen_US
dc.subjectAccumulation layersen_US
dc.subjectAccumulation modesen_US
dc.subjectBack channelsen_US
dc.subjectFully depleted silicon-on-insulatoren_US
dc.subjectJunctionlessen_US
dc.subjectJunctionless transistorsen_US
dc.subjectSOI-MOSFETsen_US
dc.subjectSystematic methodologyen_US
dc.subjectSilicon on insulator technologyen_US
dc.titleBack-gate effects and mobility characterization in junctionless transistoren_US
dc.typeJournal Articleen_US
Appears in Collections:Department of Electrical Engineering

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