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Showing results 1 to 19 of 19

Issue Date	Title	Author(s)
2015	Bacterial foraging driven exploration of multi cycle fault tolerant datapath based on power-performance tradeoff in high level synthesis	Sengupta, Anirban
2022	Cold spray-based rapid and scalable production of printed flexible electronics	Subramaniam, Karthick
2021	D flip-flop based TRNG with zero hardware cost for IoT security applications	Khan, Sajid; Shah, Ambika Prasad; Vishvakarma, Santosh Kumar
2019	Dual-Edge Triggered Lightweight Implementation of AES for IoT Security	Khan, Sajid; Gupta, Neha; Vishwakarma, Abhinav; Vishvakarma, Santosh Kumar
2014	Error masking of transient faults: Exploration of a fault tolerant datapath based on user specified power and delay budget	Sengupta, Anirban
2015	Exploration of optimal multi-cycle transient fault secured datapath during high level synthesis based on user area-delay budget	Sengupta, Anirban
2017	Finite dictionary techniques for MSER equalization in RKHS	Bhatia, Vimal
2020	Fixed Budget Kernel LMS based Estimator using Random Fourier Features	Bhatia, Vimal
2026	Hydrothermal synthesis of VO2(B) and its phase transformation to VO2(M): Investigating metal–insulator transition behavior	Kumar, Sourav
2018	Joint optimization of molecular resource allocation and relay positioning in diffusive nanonetworks	Reddy, Tadi Ravi Teja; Upadhyay, Prabhat Kumar
2020	Kernel MSER-DFE Based Post-Distorter for VLC Using Random Fourier Features	Jain, Sandesh; Bhatia, Vimal
2020	Least Minimum Symbol Error Rate Based Post-Distortion for VLC Using Random Fourier Features	Jain, Sandesh; Bhatia, Vimal
2020	Low Complexity Least Minimum Symbol Error Rate Based Post-Distortion for Vehicular VLC	Bhatia, Vimal
2022	On the origin of core radio emissions from black hole sources in the realm of relativistic shocked accretion flow	Dihingia, Indu Kalpa
2020	RFF based parallel detection for massive MIMO	Bhatia, Vimal
2015	Swarm intelligence driven design space exploration of optimal k-cycle transient fault secured datapath during high level synthesis based on user power-delay budget	Sengupta, Anirban
2020	A symmetric D flip-flop based PUF with improved uniqueness	Khan, Sajid; Shah, Ambika Prasad; Gupta, Neha; Vishvakarma, Santosh Kumar
2019	An ultra-low power, reconfigurable, aging resilient RO PUF for IoT applications	Khan, Sajid; Shah, Ambika Prasad; Gupta, Neha; Vishvakarma, Santosh Kumar
2015	User power-delay budget driven PSO based design space exploration of optimal k-cycle transient fault secured datapath during high level synthesis	Sengupta, Anirban

Showing results 1 to 19 of 19